Lines Matching +full:pcie1 +full:- +full:default +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2012 Freescale Semiconductor, Inc.
18 * Hose fields which need to be pre-initialized by board specific code:
50 u32 sz = (__ilog2_u64(size) - 1); in set_inbound_window()
59 out_be32(&pi->pitar, r->phys_start >> 12); in set_inbound_window()
60 out_be32(&pi->piwbar, r->bus_start >> 12); in set_inbound_window()
62 out_be32(&pi->piwbear, r->bus_start >> 44); in set_inbound_window()
64 out_be32(&pi->piwbear, 0); in set_inbound_window()
66 if (r->flags & PCI_REGION_PREFETCH) in set_inbound_window()
68 out_be32(&pi->piwar, flag | sz); in set_inbound_window()
75 /* Reset hose to make sure its in a clean state */ in fsl_setup_hose()
78 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); in fsl_setup_hose()
87 struct pci_region *r = hose->regions + hose->region_count; in fsl_pci_setup_inbound_windows()
88 u64 sz = min((u64)gd->ram_size, (1ull << 32)); in fsl_pci_setup_inbound_windows()
102 sz = out_lo - bus_start; in fsl_pci_setup_inbound_windows()
108 * we can overlap inbound/outbound windows on PCI-E since RX & TX in fsl_pci_setup_inbound_windows()
125 set_inbound_window(pi--, r++, sz); in fsl_pci_setup_inbound_windows()
133 set_inbound_window(pi--, r++, pci_sz); in fsl_pci_setup_inbound_windows()
135 sz -= pci_sz; in fsl_pci_setup_inbound_windows()
146 set_inbound_window(pi--, r++, pci_sz); in fsl_pci_setup_inbound_windows()
147 sz -= pci_sz; in fsl_pci_setup_inbound_windows()
155 * On 64-bit capable systems, set up a mapping for all of DRAM in fsl_pci_setup_inbound_windows()
158 pci_sz = 1ull << __ilog2_u64(gd->ram_size); in fsl_pci_setup_inbound_windows()
160 if (gd->ram_size > pci_sz) in fsl_pci_setup_inbound_windows()
161 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); in fsl_pci_setup_inbound_windows()
172 set_inbound_window(pi--, r++, pci_sz); in fsl_pci_setup_inbound_windows()
181 sz -= pci_sz; in fsl_pci_setup_inbound_windows()
184 set_inbound_window(pi--, r++, pci_sz); in fsl_pci_setup_inbound_windows()
189 if (sz && (((u64)gd->ram_size) < (1ull << 32))) in fsl_pci_setup_inbound_windows()
191 "inbound windows -- %lld remaining\n", sz); in fsl_pci_setup_inbound_windows()
194 hose->region_count = r - hose->regions; in fsl_pci_setup_inbound_windows()
202 /* configure inbound window for slave's u-boot image */ in fsl_pcie_boot_master()
203 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " in fsl_pcie_boot_master()
210 - 1; in fsl_pcie_boot_master()
217 set_inbound_window(pi--, &r_inbound, in fsl_pcie_boot_master()
220 /* configure inbound window for slave's u-boot image */ in fsl_pcie_boot_master()
221 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " in fsl_pcie_boot_master()
232 set_inbound_window(pi--, &r_inbound, in fsl_pcie_boot_master()
236 debug("PCIEBOOT - MASTER: Inbound window for slave's " in fsl_pcie_boot_master()
243 - 1; in fsl_pcie_boot_master()
250 set_inbound_window(pi--, &r_inbound, in fsl_pcie_boot_master()
276 default: in fsl_pcie_boot_master_release_slave()
283 debug("PCIEBOOT - MASTER: " in fsl_pcie_boot_master_release_slave()
286 debug("PCIEBOOT - MASTER: " in fsl_pcie_boot_master_release_slave()
294 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; in fsl_pci_init()
295 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; in fsl_pci_init()
312 struct pci_region *reg = hose->regions + hose->region_count; in fsl_pci_init()
313 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); in fsl_pci_init()
316 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ in fsl_pci_init()
319 u64 out_hi = 0, out_lo = -1ULL; in fsl_pci_init()
327 ((gd->bus_clk / 1000000) * in fsl_pci_init()
330 block_rev = in_be32(&pci->block_rev1); in fsl_pci_init()
332 pi = &pci->pit[2]; /* 0xDC0 */ in fsl_pci_init()
334 pi = &pci->pit[3]; /* 0xDE0 */ in fsl_pci_init()
338 for (r = 0; r < hose->region_count; r++) { in fsl_pci_init()
339 unsigned long flags = hose->regions[r].flags; in fsl_pci_init()
340 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); in fsl_pci_init()
344 u64 start = hose->regions[r].bus_start; in fsl_pci_init()
345 u64 end = start + hose->regions[r].size; in fsl_pci_init()
347 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); in fsl_pci_init()
348 out_be32(&po->potar, start >> 12); in fsl_pci_init()
350 out_be32(&po->potear, start >> 44); in fsl_pci_init()
352 out_be32(&po->potear, 0); in fsl_pci_init()
354 if (hose->regions[r].flags & PCI_REGION_IO) { in fsl_pci_init()
355 out_be32(&po->powar, POWAR_EN | sz | in fsl_pci_init()
358 out_be32(&po->powar, POWAR_EN | sz | in fsl_pci_init()
373 if (out_hi < (0x100000000ull - pcicsrbar_sz) || in fsl_pci_init()
375 pcicsrbar = 0x100000000ull - pcicsrbar_sz; in fsl_pci_init()
377 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; in fsl_pci_init()
386 hose->region_count++; in fsl_pci_init()
397 /* boot from PCIE --master */ in fsl_pci_init()
400 sprintf(pcie, "PCIE%d", pci_info->pci_num); in fsl_pci_init()
403 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n", in fsl_pci_init()
404 pci_info->pci_num); in fsl_pci_init()
416 for (r = 0; r < hose->region_count; r++) in fsl_pci_init()
418 (u64)hose->regions[r].phys_start, in fsl_pci_init()
419 (u64)hose->regions[r].bus_start, in fsl_pci_init()
420 (u64)hose->regions[r].size, in fsl_pci_init()
421 hose->regions[r].flags); in fsl_pci_init()
425 hose->current_busno = hose->first_busno; in fsl_pci_init()
427 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ in fsl_pci_init()
428 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except in fsl_pci_init()
429 * - Master abort (pci) in fsl_pci_init()
430 * - Master PERR (pci) in fsl_pci_init()
431 * - ICCA (PCIe) in fsl_pci_init()
449 ltssm = (in_be32(&pci->pex_csr0) in fsl_pci_init()
455 setbits_be32(&pci->pdb_stat, 0x08000000); in fsl_pci_init()
456 (void) in_be32(&pci->pdb_stat); in fsl_pci_init()
459 clrbits_be32(&pci->pdb_stat, 0x08000000); in fsl_pci_init()
478 setbits_be32(&pci->pdb_stat, 0x08000000); in fsl_pci_init()
479 (void) in_be32(&pci->pdb_stat); in fsl_pci_init()
482 &pci->pdb_stat, in_be32(&pci->pdb_stat)); in fsl_pci_init()
484 clrbits_be32(&pci->pdb_stat, 0x08000000); in fsl_pci_init()
495 /* we need to re-write the bar0 since a reset will in fsl_pci_init()
507 temp32 = in_be32(&srds_regs->srdspccr0); in fsl_pci_init()
512 out_be32(&srds_regs->srdspccr0, 2 << 28); in fsl_pci_init()
513 setbits_be32(&pci->pdb_stat, 0x08000000); in fsl_pci_init()
514 in_be32(&pci->pdb_stat); in fsl_pci_init()
516 clrbits_be32(&pci->pdb_stat, 0x08000000); in fsl_pci_init()
532 printf("undetermined, regs @ 0x%lx\n", pci_info->regs); in fsl_pci_init()
534 printf("no link, regs @ 0x%lx\n", pci_info->regs); in fsl_pci_init()
535 hose->last_busno = hose->first_busno; in fsl_pci_init()
539 out_be32(&pci->pme_msg_det, 0xffffffff); in fsl_pci_init()
540 out_be32(&pci->pme_msg_int_en, 0xffffffff); in fsl_pci_init()
545 (temp16 & 0xf), pci_info->regs); in fsl_pci_init()
547 hose->current_busno++; /* Start scan with secondary */ in fsl_pci_init()
548 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); in fsl_pci_init()
552 /* The Read-Only Write Enable bit defaults to 1 instead of 0. in fsl_pci_init()
553 * Set to 0 to protect the read-only registers. in fsl_pci_init()
555 clrbits_be32(&pci->dbi_ro_wr_en, 0x01); in fsl_pci_init()
562 pciauto_setup_device(hose, dev, 0, hose->pci_mem, in fsl_pci_init()
563 hose->pci_prefetch, hose->pci_io); in fsl_pci_init()
574 hose->current_busno); in fsl_pci_init()
575 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); in fsl_pci_init()
578 hose->current_busno, temp8); in fsl_pci_init()
579 hose->last_busno = hose->current_busno; in fsl_pci_init()
582 /* if we are PCIe - update limit regs and subordinate busno in fsl_pci_init()
586 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); in fsl_pci_init()
589 hose->last_busno = hose->current_busno; in fsl_pci_init()
594 out_be32(&pci->pme_msg_det, 0xffffffff); in fsl_pci_init()
595 out_be32(&pci->pedr, 0xffffffff); in fsl_pci_init()
612 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); in fsl_is_pci_agent()
627 * 0 == pci host or pcie root-complex, in fsl_is_pci_agent()
628 * 1 == pci agent or pcie end-point in fsl_is_pci_agent()
643 pci = (ccsr_fsl_pci_t *) pci_info->regs; in fsl_pci_init_port()
645 /* on non-PCIe controllers we don't have pme_msg_det so this code in fsl_pci_init_port()
648 if (in_be32(&pci->pme_msg_det)) { in fsl_pci_init_port()
649 out_be32(&pci->pme_msg_det, 0xffffffff); in fsl_pci_init_port()
651 pci->pme_msg_det); in fsl_pci_init_port()
654 r = hose->regions + hose->region_count; in fsl_pci_init_port()
658 pci_info->mem_bus, in fsl_pci_init_port()
659 pci_info->mem_phys, in fsl_pci_init_port()
660 pci_info->mem_size, in fsl_pci_init_port()
665 pci_info->io_bus, in fsl_pci_init_port()
666 pci_info->io_phys, in fsl_pci_init_port()
667 pci_info->io_size, in fsl_pci_init_port()
670 hose->region_count = r - hose->regions; in fsl_pci_init_port()
671 hose->first_busno = busno; in fsl_pci_init_port()
677 hose->last_busno = hose->first_busno; in fsl_pci_init_port()
680 /* boot from PCIE --master releases slave's core 0 */ in fsl_pci_init_port()
683 sprintf(pcie, "PCIE%d", pci_info->pci_num); in fsl_pci_init_port()
686 fsl_pcie_boot_master_release_slave(pci_info->pci_num); in fsl_pci_init_port()
692 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? in fsl_pci_init_port()
693 "e" : "", pci_info->pci_num, in fsl_pci_init_port()
694 hose->first_busno, hose->last_busno); in fsl_pci_init_port()
695 return(hose->last_busno + 1); in fsl_pci_init_port()
701 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); in fsl_pci_config_unlock()
712 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr; in fsl_pci_config_unlock()
713 u32 block_rev = in_be32(&pci->block_rev1); in fsl_pci_config_unlock()
714 /* PCIe - set CFG_READY bit of Configuration Ready Register */ in fsl_pci_config_unlock()
716 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY); in fsl_pci_config_unlock()
721 /* PCI - clear ACL bit of PBFR */ in fsl_pci_config_unlock()
736 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); in fsl_configure_pcie()
737 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); in fsl_configure_pcie()
739 is_endpoint = fsl_setup_hose(hose, info->regs); in fsl_configure_pcie()
740 printf("PCIe%u: %s", info->pci_num, in fsl_configure_pcie()
774 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
784 case PCIE1: in __board_serdes_name()
799 default: in __board_serdes_name()
820 int num = dev - PCIE1; in fsl_pcie_init_ctrl()
844 addr = &gur->devdisr3; in fsl_pcie_init_board()
846 addr = &gur->devdisr; in fsl_pcie_init_board()
852 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); in fsl_pcie_init_board()
908 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; in ft_fsl_pci_setup()
917 if ((hose == NULL) || (hose->cfg_addr == NULL)) { in ft_fsl_pci_setup()
921 bus_range[1] = hose->last_busno - hose->first_busno; in ft_fsl_pci_setup()
922 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); in ft_fsl_pci_setup()