83 static volatile emac_regs	*adap_emac = (emac_regs *)EMAC_BASE_ADDR;  variable
120 	writel(0, &adap_emac->MACINDEX);  in davinci_eth_set_mac_addr()
128 	writel(mac_hi, &adap_emac->MACADDRHI);  in davinci_eth_set_mac_addr()
131 	       &adap_emac->MACADDRLO);  in davinci_eth_set_mac_addr()
133 	writel(mac_lo, &adap_emac->MACADDRLO);  in davinci_eth_set_mac_addr()
136 	writel(0, &adap_emac->MACHASH1);  in davinci_eth_set_mac_addr()
137 	writel(0, &adap_emac->MACHASH2);  in davinci_eth_set_mac_addr()
140 	writel(mac_hi, &adap_emac->MACSRCADDRHI);  in davinci_eth_set_mac_addr()
141 	writel(mac_lo, &adap_emac->MACSRCADDRLO);  in davinci_eth_set_mac_addr()
298 					&adap_emac->MACCONTROL);  in gen_get_link_speed()
302 					&adap_emac->MACCONTROL);  in gen_get_link_speed()
306 			writel(readl(&adap_emac->MACCONTROL) |  in gen_get_link_speed()
308 					 &adap_emac->MACCONTROL);  in gen_get_link_speed()
310 			writel(readl(&adap_emac->MACCONTROL) &  in gen_get_link_speed()
312 					 &adap_emac->MACCONTROL);  in gen_get_link_speed()
405 			writel(readl(&adap_emac->MACCONTROL) |  in davinci_eth_gigabit_enable()
408 				&adap_emac->MACCONTROL);  in davinci_eth_gigabit_enable()
425 	writel(1, &adap_emac->SOFTRESET);  in davinci_eth_open()
426 	while (readl(&adap_emac->SOFTRESET) != 0)  in davinci_eth_open()
447 	writel(1, &adap_emac->TXCONTROL);  in davinci_eth_open()
448 	writel(1, &adap_emac->RXCONTROL);  in davinci_eth_open()
453 	addr = &adap_emac->TX0HDP;  in davinci_eth_open()
457 	addr = &adap_emac->RX0HDP;  in davinci_eth_open()
462 	addr = &adap_emac->RXGOODFRAMES;  in davinci_eth_open()
467 	writel(0, &adap_emac->MACHASH1);  in davinci_eth_open()
468 	writel(0, &adap_emac->MACHASH2);  in davinci_eth_open()
487 	writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);  in davinci_eth_open()
488 	writel(0, &adap_emac->RXBUFFEROFFSET);  in davinci_eth_open()
494 	writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);  in davinci_eth_open()
497 	writel(1, &adap_emac->RXUNICASTSET);  in davinci_eth_open()
530 	writel(mac_control, &adap_emac->MACCONTROL);  in davinci_eth_open()
532 	writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);  in davinci_eth_open()
549 		writel(0, &adap_emac->TXTEARDOWN);  in davinci_eth_ch_teardown()
562 			cnt = readl(&adap_emac->TX0CP);  in davinci_eth_ch_teardown()
564 		writel(cnt, &adap_emac->TX0CP);  in davinci_eth_ch_teardown()
565 		writel(0, &adap_emac->TX0HDP);  in davinci_eth_ch_teardown()
568 		writel(0, &adap_emac->RXTEARDOWN);  in davinci_eth_ch_teardown()
581 			cnt = readl(&adap_emac->RX0CP);  in davinci_eth_ch_teardown()
583 		writel(cnt, &adap_emac->RX0CP);  in davinci_eth_ch_teardown()
584 		writel(0, &adap_emac->RX0HDP);  in davinci_eth_ch_teardown()
596 	if (readl(&adap_emac->RXCONTROL) & 1)  in davinci_eth_close()
600 	writel(1, &adap_emac->SOFTRESET);  in davinci_eth_close()
653 	writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);  in davinci_eth_send_packet()
662 		if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {  in davinci_eth_send_packet()
701 		writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);  in davinci_eth_rcv_packet()
709 				       &adap_emac->RX0HDP);  in davinci_eth_rcv_packet()
727 				       &adap_emac->RX0HDP);  in davinci_eth_rcv_packet()
738 				       &adap_emac->RX0HDP);  in davinci_eth_rcv_packet()