Lines Matching full:r
104 #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
108 #define INT_CFG_IRQ_EN 0x00000100 /* R/W */
109 /* R/W Not Affected by SW Reset */
111 /* R/W Not Affected by SW Reset */
115 #define INT_STS_SW_INT 0x80000000 /* R/WC */
116 #define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
117 #define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
118 #define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
119 #define INT_STS_RXDF_INT 0x00400000 /* R/WC */
120 #define INT_STS_TX_IOC 0x00200000 /* R/WC */
121 #define INT_STS_RXD_INT 0x00100000 /* R/WC */
122 #define INT_STS_GPT_INT 0x00080000 /* R/WC */
124 #define INT_STS_PME_INT 0x00020000 /* R/WC */
125 #define INT_STS_TXSO 0x00010000 /* R/WC */
126 #define INT_STS_RWT 0x00008000 /* R/WC */
127 #define INT_STS_RXE 0x00004000 /* R/WC */
128 #define INT_STS_TXE 0x00002000 /* R/WC */
129 /*#define INT_STS_ERX 0x00001000*/ /* R/WC */
130 #define INT_STS_TDFU 0x00000800 /* R/WC */
131 #define INT_STS_TDFO 0x00000400 /* R/WC */
132 #define INT_STS_TDFA 0x00000200 /* R/WC */
133 #define INT_STS_TSFF 0x00000100 /* R/WC */
134 #define INT_STS_TSFL 0x00000080 /* R/WC */
135 /*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
136 #define INT_STS_RDFO 0x00000040 /* R/WC */
137 #define INT_STS_RDFL 0x00000020 /* R/WC */
138 #define INT_STS_RSFF 0x00000010 /* R/WC */
139 #define INT_STS_RSFL 0x00000008 /* R/WC */
140 #define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
141 #define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
142 #define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
144 #define INT_EN_SW_INT_EN 0x80000000 /* R/W */
145 #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
146 #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
147 #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
148 /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
149 #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
150 #define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
151 #define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
152 #define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
153 #define INT_EN_PME_INT_EN 0x00020000 /* R/W */
154 #define INT_EN_TXSO_EN 0x00010000 /* R/W */
155 #define INT_EN_RWT_EN 0x00008000 /* R/W */
156 #define INT_EN_RXE_EN 0x00004000 /* R/W */
157 #define INT_EN_TXE_EN 0x00002000 /* R/W */
158 /*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
159 #define INT_EN_TDFU_EN 0x00000800 /* R/W */
160 #define INT_EN_TDFO_EN 0x00000400 /* R/W */
161 #define INT_EN_TDFA_EN 0x00000200 /* R/W */
162 #define INT_EN_TSFF_EN 0x00000100 /* R/W */
163 #define INT_EN_TSFL_EN 0x00000080 /* R/W */
164 /*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
165 #define INT_EN_RDFO_EN 0x00000040 /* R/W */
166 #define INT_EN_RDFL_EN 0x00000020 /* R/W */
167 #define INT_EN_RSFF_EN 0x00000010 /* R/W */
168 #define INT_EN_RSFL_EN 0x00000008 /* R/W */
169 #define INT_EN_GPIO2_INT 0x00000004 /* R/W */
170 #define INT_EN_GPIO1_INT 0x00000002 /* R/W */
171 #define INT_EN_GPIO0_INT 0x00000001 /* R/W */
175 #define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
176 #define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
177 #define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
178 #define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
181 #define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
182 #define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
183 #define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
184 #define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
185 #define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
186 #define RX_CFG_RX_DUMP 0x00008000 /* R/W */
187 #define RX_CFG_RXDOFF 0x00001F00 /* R/W */
188 /*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
191 /*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
192 /* R/W Self Clearing */
196 #define TX_CFG_TXSAO 0x00000004 /* R/W */
197 #define TX_CFG_TX_ON 0x00000002 /* R/W */
201 #define HW_CFG_TTM 0x00200000 /* R/W */
202 #define HW_CFG_SF 0x00100000 /* R/W */
203 #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
204 #define HW_CFG_TR 0x00003000 /* R/W */
205 #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
206 #define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
207 #define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
208 #define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
209 #define HW_CFG_SMI_SEL 0x00000010 /* R/W */
211 #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
217 #define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
231 #define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
232 #define PMT_CTRL_ED_EN 0x00000100 /* R/W */
233 /* R/W Not Affected by SW Reset */
235 #define PMT_CTRL_WUPS 0x00000030 /* R/WC */
236 #define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
237 #define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
238 #define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
239 #define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
240 #define PMT_CTRL_PME_IND 0x00000008 /* R/W */
241 #define PMT_CTRL_PME_POL 0x00000004 /* R/W */
242 /* R/W Not Affected by SW Reset */
247 #define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
248 #define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
249 #define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
250 #define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
251 #define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
252 #define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
253 #define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
254 #define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
255 #define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
256 #define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
257 #define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
258 #define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
259 #define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
260 #define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
261 #define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
262 #define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
263 #define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
264 #define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
267 #define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
268 #define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
278 #define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
279 #define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
283 #define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
284 #define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
285 #define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
286 #define AFC_CFG_FCMULT 0x00000008 /* R/W */
287 #define AFC_CFG_FCBRD 0x00000004 /* R/W */
288 #define AFC_CFG_FCADD 0x00000002 /* R/W */
289 #define AFC_CFG_FCANY 0x00000001 /* R/W */
293 #define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
294 #define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
295 #define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
296 #define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
297 #define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
298 #define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
299 #define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
300 #define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
301 #define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
304 #define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
307 #define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
311 #define MAC_CR 0x01 /* R/W */
335 #define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
336 #define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
337 #define HASHH 0x04 /* R/W */
338 #define HASHL 0x05 /* R/W */
340 #define MII_ACC 0x06 /* R/W */
346 #define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
348 #define FLOW 0x08 /* R/W */
354 #define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
357 #define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
362 #define WUCSR 0x0C /* R/W */