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13 . the LAN91C111 single chip ethernet controller. It is a modified
17 . manual from SMC. To get a copy, if you really want one, you can find
22 . Daris A Nevil ( dnevil@snmc.com )
25 . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
56 . 1 for slightly more details
71 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) argument
72 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) argument
73 #define SMC_inb(a,p) ({ \ argument
74 unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
80 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) argument
81 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) argument
82 #define SMC_inb(a,p) ({ \ argument
83 unsigned int __p = (unsigned int)((a)->iobase + (p)); \
84 unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
85 if (__p & 1) __v >>= 8; \
91 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) argument
92 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) argument
94 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) argument
95 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) argument
98 #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ argument
99 word __w = SMC_inw((a),(r)&~1); \
100 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
101 __w |= ((r)&1) ? __d<<8 : __d; \
102 SMC_outw((a),__w,(r)&~1); \
105 #define SMC_outsl(a,r,b,l) ({ int __i; \ argument
109 SMC_outl((a), *(__b2 + __i), r); \
113 #define SMC_outsw(a,r,b,l) ({ int __i; \ argument
117 SMC_outw((a), *(__b2 + __i), r); \
121 #define SMC_insl(a,r,b,l) ({ int __i ; \ argument
125 *(__b2 + __i) = SMC_inl((a),(r)); \
126 SMC_inl((a),0); \
130 #define SMC_insw(a,r,b,l) ({ int __i ; \ argument
134 *(__b2 + __i) = SMC_inw((a),(r)); \
135 SMC_inw((a),0); \
139 #define SMC_insb(a,r,b,l) ({ int __i ; \ argument
143 *(__b2 + __i) = SMC_inb((a),(r)); \
144 SMC_inb((a),0); \
159 #define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) argument
160 #define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) argument
161 #define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) argument
162 #define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) argument
163 #define SMC_inb(a,p) ({ \ argument
164 word ___v = SMC_inw((a),(p) & ~1); \
165 if ((p) & 1) ___v >>= 8; \
169 #define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) argument
170 #define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) argument
171 #define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) argument
172 #define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) argument
173 #define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ argument
174 word __w = SMC_inw((a),(r)&~1); \
175 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
176 __w |= ((r)&1) ? __d<<8 : __d; \
177 SMC_outw((a),__w,(r)&~1); \
179 #define SMC_outsl(a,r,b,l) do{ int __i; \ argument
183 SMC_outl_nosw((a), *(__b2 + __i), r); \
186 #define SMC_outsw(a,r,b,l) do{ int __i; \ argument
190 SMC_outw_nosw((a), *(__b2 + __i), r); \
193 #define SMC_insl(a,r,b,l) do{ int __i ; \ argument
197 *(__b2 + __i) = SMC_inl_nosw((a),(r)); \
201 #define SMC_insw(a,r,b,l) do{ int __i ; \ argument
205 *(__b2 + __i) = SMC_inw_nosw((a),(r)); \
209 #define SMC_insb(a,r,b,l) do{ int __i ; \ argument
213 *(__b2 + __i) = SMC_inb((a),(r)); \
218 #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) argument
219 #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) argument
220 #define SMC_insw(a, r, b, l) \ argument
225 *__b2++ = SWAB7206(SMC_inw(a, r)); \
228 #define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) argument
229 #define SMC_outb(a, d, r) ({ word __d = (byte)(d); \ argument
230 word __w = SMC_inw((a), ((r)&(~1))); \
231 if (((r) & 1)) \
235 SMC_outw((a), __w, ((r)&(~1))); \
237 #define SMC_outsw(a, r, b, l) \ argument
242 SMC_outw(a, SWAB7206(*__b2), r); \
254 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) argument
256 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) argument
258 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) argument
260 #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) argument
263 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) argument
265 #define SMC_outw(a, d, r) \ argument
266 (*((volatile word*)((a)->iobase+((dword)(r)))) = d)
268 #define SMC_outw(a, d, r) \ argument
269 (*((volatile word*)((a)->iobase+(r))) = d)
271 #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ argument
272 word __w = SMC_inw((a),(r)&~1); \
273 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
274 __w |= ((r)&1) ? __d<<8 : __d; \
275 SMC_outw((a),__w,(r)&~1); \
278 #define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l))
280 #define SMC_outsw(a,r,b,l) ({ int __i; \ argument
284 SMC_outw((a), *(__b2 + __i), r); \
290 #define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l))
292 #define SMC_insw(a,r,b,l) ({ int __i ; \ argument
296 *(__b2 + __i) = SMC_inw((a),(r)); \
297 SMC_inw((a),0); \
307 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) argument
309 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) argument
312 #define SMC_insl(a,r,b,l) ({ int __i ; \ argument
316 *(__b2 + __i) = SMC_inl((a),(r)); \
317 SMC_inl((a),0); \
322 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) argument
324 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) argument
326 #define SMC_outsl(a,r,b,l) ({ int __i; \ argument
330 SMC_outl((a), *(__b2 + __i), r); \
340 . A description of the SMSC registers is probably in order here,
344 . are accessed by writing a number into the BANK_SELECT register
345 . ( I also use a SMC_SELECT_BANK macro for this ).
363 #define TCR_ENABLE 0x0001 /* When 1 we can transmit */
365 #define TCR_FORCOL 0x0004 /* When 1 will force a collision */
366 #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
367 #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
368 #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
369 #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
370 #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
371 #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
372 #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
386 #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
389 #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
402 #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
413 #define RCR_CLEAR 0x0 /* set it to a base state */
426 #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
427 #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
428 #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
464 /* BANK 1 */
466 #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
468 #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
476 /* BANK 1 */
481 /* BANK 1 */
488 /* BANK 1 */
493 /* BANK 1 */
495 #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
496 #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
497 #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
498 #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
499 #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
508 #define MC_BUSY 1 /* When 1 the last release has not completed */
510 #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
532 #define RXFIFO_REG 0x0004 /* Must be read as a word */
538 #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
545 #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
547 #define PTR_READ 0x2000 /* When 1 the operation is a read */
548 #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */
601 #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
654 PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
663 #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
664 #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
665 #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
666 #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
667 #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
668 #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
669 #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
670 #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
671 #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
675 #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
676 #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
677 #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
678 #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
679 #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
680 #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
681 #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
682 #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
683 #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
684 #define PHY_STAT_LINK 0x0004 /* 1=valid link */
685 #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
686 #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
689 #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
694 #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
695 #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
696 #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
697 #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
698 #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
699 #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
700 #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
701 #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
702 #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
708 /* PHY Configuration Register 1 */
710 #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
711 #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
712 #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
713 #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
714 #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
715 #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
716 #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
717 #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
725 #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
726 #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
727 #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
728 #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
732 #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
733 #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
734 #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
735 #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
736 #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
737 #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
738 #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
739 #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
740 #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
741 #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
753 /* select a register bank, 0 to 3 */
755 #define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } argument
758 #define SMC_ENABLE_INT(a,x) {\ argument
760 SMC_SELECT_BANK((a),2);\
761 mask = SMC_inb((a), IM_REG );\
763 SMC_outb( (a), mask, IM_REG ); \
768 #define SMC_DISABLE_INT(a,x) {\ argument
771 mask = SMC_inb( (a), IM_REG );\
773 SMC_outb( (a), mask, IM_REG ); \