1 // SPDX-License-Identifier: GPL-2.0
3  * TI PHY drivers
7 #include <phy.h>
12 #include <dt-bindings/net/ti-dp83867.h>
55 /* PHY CTRL bits */
82 #define MII_MMD_CTRL_NOINCR	0x4000 /* no post increment */
86 /* User setting - can be taken from DTS */
120  * phy_read_mmd_indirect - reads data from the MMD registers
121  * @phydev: The PHY device bus
124  * @addr: PHY address on the MII bus
127  * clause 45) of the specified phy address.
137 	int value = -1;  in phy_read_mmd_indirect()
145 	/* Select the Function : DATA with no post increment */  in phy_read_mmd_indirect()
154  * phy_write_mmd_indirect - writes data to the MMD registers
155  * @phydev: The PHY device
158  * @addr: PHY address on the MII bus
162  * phy address.
178 	/* Select the Function : DATA with no post increment */  in phy_write_mmd_indirect()
188 		(struct dp83867_private *)phydev->priv;  in dp83867_config_port_mirroring()
192 				    phydev->addr);  in dp83867_config_port_mirroring()
194 	if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)  in dp83867_config_port_mirroring()
200 			       phydev->addr, val);  in dp83867_config_port_mirroring()
207  * dp83867_data_init - Convenience function for setting PHY specific data
213 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_of_init()
220 	 * Keep the default value if ti,clk-output-sel is not set  in dp83867_of_init()
224 	dp83867->clk_output_sel =  in dp83867_of_init()
225 		ofnode_read_u32_default(node, "ti,clk-output-sel",  in dp83867_of_init()
230 		return -EINVAL;  in dp83867_of_init()
232 	if (ofnode_read_bool(node, "ti,max-output-impedance"))  in dp83867_of_init()
233 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;  in dp83867_of_init()
234 	else if (ofnode_read_bool(node, "ti,min-output-impedance"))  in dp83867_of_init()
235 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;  in dp83867_of_init()
237 		dp83867->io_impedance = -EINVAL;  in dp83867_of_init()
239 	if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))  in dp83867_of_init()
240 		dp83867->rxctrl_strap_quirk = true;  in dp83867_of_init()
241 	dp83867->rx_id_delay = ofnode_read_u32_default(node,  in dp83867_of_init()
242 						       "ti,rx-internal-delay",  in dp83867_of_init()
243 						       -1);  in dp83867_of_init()
245 	dp83867->tx_id_delay = ofnode_read_u32_default(node,  in dp83867_of_init()
246 						       "ti,tx-internal-delay",  in dp83867_of_init()
247 						       -1);  in dp83867_of_init()
249 	dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",  in dp83867_of_init()
250 						      -1);  in dp83867_of_init()
251 	if (ofnode_read_bool(node, "enet-phy-lane-swap"))  in dp83867_of_init()
252 		dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;  in dp83867_of_init()
254 	if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))  in dp83867_of_init()
255 		dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;  in dp83867_of_init()
259 	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {  in dp83867_of_init()
261 					    DP83867_DEVADDR, phydev->addr);  in dp83867_of_init()
263 		val |= (dp83867->clk_output_sel <<  in dp83867_of_init()
266 				       DP83867_DEVADDR, phydev->addr, val);  in dp83867_of_init()
274 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_of_init()
276 	dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;  in dp83867_of_init()
277 	dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;  in dp83867_of_init()
278 	dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;  in dp83867_of_init()
279 	dp83867->io_impedance = -EINVAL;  in dp83867_of_init()
291 	if (!phydev->priv) {  in dp83867_config()
294 			return -ENOMEM;  in dp83867_config()
296 		phydev->priv = dp83867;  in dp83867_config()
301 		dp83867 = (struct dp83867_private *)phydev->priv;  in dp83867_config()
304 	/* Restart the PHY.  */  in dp83867_config()
310 	if (dp83867->rxctrl_strap_quirk) {  in dp83867_config()
312 					    DP83867_DEVADDR, phydev->addr);  in dp83867_config()
315 				       DP83867_DEVADDR, phydev->addr, val);  in dp83867_config()
321 			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));  in dp83867_config()
328 		 * Such N/A mode enabled by mistake can put PHY IC in some  in dp83867_config()
336 					   DP83867_DEVADDR, phydev->addr);  in dp83867_config()
348 		cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);  in dp83867_config()
358 				       DP83867_DEVADDR, phydev->addr, 0x0);  in dp83867_config()
364 			  (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |  in dp83867_config()
365 			  (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));  in dp83867_config()
371 					    DP83867_DEVADDR, phydev->addr);  in dp83867_config()
373 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)  in dp83867_config()
377 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)  in dp83867_config()
380 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)  in dp83867_config()
384 				       DP83867_DEVADDR, phydev->addr, val);  in dp83867_config()
386 		delay = (dp83867->rx_id_delay |  in dp83867_config()
387 			 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));  in dp83867_config()
390 				       DP83867_DEVADDR, phydev->addr, delay);  in dp83867_config()
392 		if (dp83867->io_impedance >= 0) {  in dp83867_config()
396 						    phydev->addr);  in dp83867_config()
398 			val |= dp83867->io_impedance &  in dp83867_config()
401 					       DP83867_DEVADDR, phydev->addr,  in dp83867_config()
406 	if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)  in dp83867_config()