Lines Matching refs:reg_val
287 u16 reg_val; in vsc8584_cmd() local
297 reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE, in vsc8584_cmd()
300 (reg_val & PROC_CMD_NCOMPLETED) && in vsc8584_cmd()
301 !(reg_val & PROC_CMD_FAILED)); in vsc8584_cmd()
306 if (reg_val & PROC_CMD_FAILED) in vsc8584_cmd()
308 if (reg_val & PROC_CMD_NCOMPLETED) in vsc8584_cmd()
1010 u16 reg_val; in mscc_vsc8531_vsc8541_init_scripts() local
1020 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
1021 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS, in mscc_vsc8531_vsc8541_init_scripts()
1025 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
1034 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
1035 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGATHRESH100_POS, in mscc_vsc8531_vsc8541_init_scripts()
1039 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
1048 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
1049 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_U_POS, in mscc_vsc8531_vsc8541_init_scripts()
1053 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
1054 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
1055 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_L_POS, in mscc_vsc8531_vsc8541_init_scripts()
1059 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
1119 u16 reg_val = 0; in mscc_phy_soft_reset() local
1124 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
1125 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET)); in mscc_phy_soft_reset()
1127 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
1129 while ((reg_val & BMCR_RESET) && (timeout > 0)) { in mscc_phy_soft_reset()
1130 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
1146 u16 reg_val = 0; in vsc8531_vsc8541_mac_config() local
1185 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
1188 reg_val = bitfield_replace(reg_val, MAC_IF_SELECTION_POS, in vsc8531_vsc8541_mac_config()
1192 MSCC_PHY_EXT_PHY_CNTL_1_REG, reg_val); in vsc8531_vsc8541_mac_config()
1197 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
1199 reg_val = bitfield_replace(reg_val, RX_CLK_OUT_POS, in vsc8531_vsc8541_mac_config()
1203 MSCC_PHY_RGMII_CNTL_REG, reg_val); in vsc8531_vsc8541_mac_config()
1214 u16 reg_val; in vsc8531_config() local
1245 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG); in vsc8531_config()
1248 reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS, in vsc8531_config()
1251 reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS, in vsc8531_config()
1254 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val); in vsc8531_config()
1256 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL); in vsc8531_config()
1258 reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS, in vsc8531_config()
1261 reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS, in vsc8531_config()
1264 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc8531_config()
1274 u16 reg_val; in vsc8541_config() local
1307 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG); in vsc8541_config()
1309 reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS, in vsc8541_config()
1312 reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS, in vsc8541_config()
1314 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val); in vsc8541_config()
1316 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL); in vsc8541_config()
1318 reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS, in vsc8541_config()
1321 reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS, in vsc8541_config()
1324 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc8541_config()
1336 u16 reg_val; in vsc8584_config_init() local
1356 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8584_config_init()
1357 reg_val &= ~MAC_CFG_MASK; in vsc8584_config_init()
1358 reg_val |= val; in vsc8584_config_init()
1360 reg_val); in vsc8584_config_init()
1364 reg_val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | in vsc8584_config_init()
1367 reg_val |= PROC_CMD_QSGMII_MAC; in vsc8584_config_init()
1369 reg_val |= PROC_CMD_SGMII_MAC; in vsc8584_config_init()
1371 ret = vsc8584_cmd(phydev->bus, phydev->addr, reg_val); in vsc8584_config_init()
1395 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8584_config_init()
1397 reg_val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); in vsc8584_config_init()
1398 reg_val |= MEDIA_OP_MODE_COPPER | in vsc8584_config_init()
1402 reg_val); in vsc8584_config_init()