1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2015-2016 Freescale Semiconductor, Inc.
35 			(u32)TMU_DMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);  in pfe_lib_init()
37 			(u32)TMU_IMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);  in pfe_lib_init()
118 				- 1)) | PE_MEM_ACCESS_IMEM, src, len);  in pe_pmem_memcpy_to32()
134 	u32 mask = 0xffffffff >> ((4 - size) << 3);  in pe_pmem_read()
137 	addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))  in pe_pmem_read()
182 	u32 mask = 0xffffffff >> ((4 - size) << 3);  in pe_dmem_read()
198  * pe-lem) from the host
219  * Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
228 	u32 mask = 0xffffffff >> ((4 - size) << 3);  in class_bus_read()
349 	u32 offset = be32_to_cpu(shdr->sh_offset);  in pe_load_pmem_section()
350 	u32 addr = be32_to_cpu(shdr->sh_addr);  in pe_load_pmem_section()
351 	u32 size = be32_to_cpu(shdr->sh_size);  in pe_load_pmem_section()
352 	u32 type = be32_to_cpu(shdr->sh_type);  in pe_load_pmem_section()
359 		return -1;  in pe_load_pmem_section()
365 		return -1;  in pe_load_pmem_section()
371 		return -1;  in pe_load_pmem_section()
382 		return -1;  in pe_load_pmem_section()
400 	u32 offset = be32_to_cpu(shdr->sh_offset);  in pe_load_dmem_section()
401 	u32 addr = be32_to_cpu(shdr->sh_addr);  in pe_load_dmem_section()
402 	u32 size = be32_to_cpu(shdr->sh_size);  in pe_load_dmem_section()
403 	u32 type = be32_to_cpu(shdr->sh_type);  in pe_load_dmem_section()
412 		return -1;  in pe_load_dmem_section()
418 		return -1;  in pe_load_dmem_section()
439 		return -1;  in pe_load_dmem_section()
457 	u32 offset = be32_to_cpu(shdr->sh_offset);  in pe_load_ddr_section()
458 	u32 addr = be32_to_cpu(shdr->sh_addr);  in pe_load_ddr_section()
459 	u32 size = be32_to_cpu(shdr->sh_size);  in pe_load_ddr_section()
460 	u32 type = be32_to_cpu(shdr->sh_type);  in pe_load_ddr_section()
461 	u32 flags = be32_to_cpu(shdr->sh_flags);  in pe_load_ddr_section()
482 						return -1;  in pe_load_ddr_section()
489 						return -1;  in pe_load_ddr_section()
496 						return -1;  in pe_load_ddr_section()
506 				return -1;  in pe_load_ddr_section()
524 		return -1;  in pe_load_ddr_section()
541 	u32 offset = be32_to_cpu(shdr->sh_offset);  in pe_load_pe_lmem_section()
542 	u32 addr = be32_to_cpu(shdr->sh_addr);  in pe_load_pe_lmem_section()
543 	u32 size = be32_to_cpu(shdr->sh_size);  in pe_load_pe_lmem_section()
544 	u32 type = be32_to_cpu(shdr->sh_type);  in pe_load_pe_lmem_section()
547 		printf("%s: unsupported pe-lmem section type(%x) for PE(%d)\n",  in pe_load_pe_lmem_section()
549 		return -1;  in pe_load_pe_lmem_section()
557 		return -1;  in pe_load_pe_lmem_section()
563 		return -1;  in pe_load_pe_lmem_section()
579 		return -1;  in pe_load_pe_lmem_section()
588  * tmu PE's), DDDR (util PE code)
596 	u32 addr = be32_to_cpu(shdr->sh_addr);  in pe_load_elf_section()
597 	u32 size = be32_to_cpu(shdr->sh_size);  in pe_load_elf_section()
610 	printf("%s: unsupported memory range(%x)\n", __func__, addr);  in pe_load_elf_section()
654 	writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);  in bmu_set_config()
655 	writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);  in bmu_set_config()
656 	writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);  in bmu_set_config()
727 	writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |  in gpi_set_config()
729 	writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);  in gpi_set_config()
730 	writel(cfg->aseq_len, base + GPI_DTX_ASEQ);  in gpi_set_config()
732 	/*Make GPI AXI transactions non-bufferable */  in gpi_set_config()
760  * Enables all CLASS-PE's cores.
768  * Disables all CLASS-PE's cores.
791 		CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),  in class_set_config()
795 	writel(cfg->route_table_baseaddr, CLASS_ROUTE_TABLE_BASE);  in class_set_config()
796 	memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0,  in class_set_config()
811 	/*Make Class AXI transactions non-bufferable */  in class_set_config()
814 	/*Make Util AXI transactions non-bufferable */  in class_set_config()
815 	/*Util is disabled in U-boot, do it from here */  in class_set_config()
832 /**************************** TMU ***************************/
834  * Enables TMU-PE cores.
835  * @param[in] pe_mask	TMU PE mask
843  * Disables TMU cores.
844  * @param[in] pe_mask	TMU PE mask
852  * Initializes TMU block.
853  * @param[in] cfg	TMU configuration
862 	/*Make Class AXI transactions non-bufferable */  in tmu_init()
896 	debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);  in tmu_init()
897 	writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR);  in tmu_init()
899 	debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);  in tmu_init()
900 	writel(cfg->llm_queue_len,	TMU_LLM_QUE_LEN);  in tmu_init()
996 	/* Make HIF AXI transactions non-bufferable */  in hif_init()