Lines Matching +full:gop +full:- +full:port +full:- +full:id
8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
68 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
69 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
74 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
95 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
96 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
97 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
98 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
99 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
100 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
101 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
102 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
115 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) argument
125 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) argument
128 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) argument
130 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) argument
235 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) argument
238 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) argument
247 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) argument
336 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) argument
346 /* Per-port registers */
392 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
393 * relative to port->base.
396 /* Port Mac Control0 */
402 /* Port Mac Control1 */
406 /* Port Interrupt Mask */
409 /* Port Mac Control3 */
414 /* Port Mac Control4 */
484 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \ argument
485 (0x4 * (port)))
491 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
493 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
495 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
586 /* Maximum number of T-CONTs of PON port */
592 /* Maximum number of TXQs used by single port */
618 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
650 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
657 /* Port flags */
693 * - lookup ID - 4 bits
694 * - port ID - 1 byte
695 * - additional information - 1 byte
696 * - header data - 8 bytes
697 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
703 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
705 (((offs) * 2) - ((offs) % 2) + 2)
711 /* Tcam entries ID */
714 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
715 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
716 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
717 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
718 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
719 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
720 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
721 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
722 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
723 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
724 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
725 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
726 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
727 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
728 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
729 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
730 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
731 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
732 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
733 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
734 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
735 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
736 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
737 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
738 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
741 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
842 /* Lookup ID */
872 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
874 #define MVPP2_BM_SWF_LONG_POOL(port) 0 argument
907 /* List of pointers to port structures */
927 /* Maximum number of RXQs per port */
942 u8 id; member
944 /* Index of the port from the "group of ports" complex point
953 /* Per-port registers' base address */
964 /* Per-CPU port control */
993 /* Index of first port's physical RXQ */
1035 u8 phys_txq; /* destination queue ID */
1098 /* Per-CPU Tx queue control */
1122 u8 id; member
1133 /* Per-CPU control of physical Tx queues */
1152 /* RX queue number, in the range 0-31 for physical RXQs */
1153 u8 id; member
1173 /* ID of port to which physical RXQ is mapped */
1174 int port; member
1176 /* Port's logic RXQ number to which physical RXQ is mapped */
1200 /* Lookup ID */
1223 /* Pool number in the range 0-7 */
1224 int id; member
1247 /* Number of RXQs used by single port */
1249 /* Number of TXQs used by single port */
1258 * U-Boot internal data, mostly uncached buffers for descriptors and data
1285 writel(data, priv->base + offset); in mvpp2_write()
1290 return readl(priv->base + offset); in mvpp2_read()
1293 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_set() argument
1297 if (port->priv->hw_version == MVPP21) { in mvpp2_txdesc_dma_addr_set()
1298 tx_desc->pp21.buf_dma_addr = dma_addr; in mvpp2_txdesc_dma_addr_set()
1302 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); in mvpp2_txdesc_dma_addr_set()
1303 tx_desc->pp22.buf_dma_addr_ptp |= val; in mvpp2_txdesc_dma_addr_set()
1307 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, in mvpp2_txdesc_size_set() argument
1311 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_set()
1312 tx_desc->pp21.data_size = size; in mvpp2_txdesc_size_set()
1314 tx_desc->pp22.data_size = size; in mvpp2_txdesc_size_set()
1317 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, in mvpp2_txdesc_txq_set() argument
1321 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_txq_set()
1322 tx_desc->pp21.phys_txq = txq; in mvpp2_txdesc_txq_set()
1324 tx_desc->pp22.phys_txq = txq; in mvpp2_txdesc_txq_set()
1327 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, in mvpp2_txdesc_cmd_set() argument
1331 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_cmd_set()
1332 tx_desc->pp21.command = command; in mvpp2_txdesc_cmd_set()
1334 tx_desc->pp22.command = command; in mvpp2_txdesc_cmd_set()
1337 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, in mvpp2_txdesc_offset_set() argument
1341 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_offset_set()
1342 tx_desc->pp21.packet_offset = offset; in mvpp2_txdesc_offset_set()
1344 tx_desc->pp22.packet_offset = offset; in mvpp2_txdesc_offset_set()
1347 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_rxdesc_dma_addr_get() argument
1350 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_dma_addr_get()
1351 return rx_desc->pp21.buf_dma_addr; in mvpp2_rxdesc_dma_addr_get()
1353 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); in mvpp2_rxdesc_dma_addr_get()
1356 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, in mvpp2_rxdesc_cookie_get() argument
1359 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_cookie_get()
1360 return rx_desc->pp21.buf_cookie; in mvpp2_rxdesc_cookie_get()
1362 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); in mvpp2_rxdesc_cookie_get()
1365 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, in mvpp2_rxdesc_size_get() argument
1368 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_size_get()
1369 return rx_desc->pp21.data_size; in mvpp2_rxdesc_size_get()
1371 return rx_desc->pp22.data_size; in mvpp2_rxdesc_size_get()
1374 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, in mvpp2_rxdesc_status_get() argument
1377 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_status_get()
1378 return rx_desc->pp21.status; in mvpp2_rxdesc_status_get()
1380 return rx_desc->pp22.status; in mvpp2_rxdesc_status_get()
1385 txq_pcpu->txq_get_index++; in mvpp2_txq_inc_get()
1386 if (txq_pcpu->txq_get_index == txq_pcpu->size) in mvpp2_txq_inc_get()
1387 txq_pcpu->txq_get_index = 0; in mvpp2_txq_inc_get()
1390 /* Get number of physical egress port */
1391 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
1393 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
1397 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
1399 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
1409 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
1410 return -EINVAL; in mvpp2_prs_hw_write()
1413 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1415 /* Write tcam index - indirect access */ in mvpp2_prs_hw_write()
1416 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1418 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1420 /* Write sram index - indirect access */ in mvpp2_prs_hw_write()
1421 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1423 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1433 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1434 return -EINVAL; in mvpp2_prs_hw_read()
1436 /* Write tcam index - indirect access */ in mvpp2_prs_hw_read()
1437 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1439 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_hw_read()
1441 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_hw_read()
1445 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1447 /* Write sram index - indirect access */ in mvpp2_prs_hw_read()
1448 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1450 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1458 /* Write index - indirect access */ in mvpp2_prs_hw_inv()
1464 /* Enable shadow table entry and set its lookup ID */
1467 priv->prs_shadow[index].valid = true; in mvpp2_prs_shadow_set()
1468 priv->prs_shadow[index].lu = lu; in mvpp2_prs_shadow_set()
1475 priv->prs_shadow[index].ri_mask = ri_mask; in mvpp2_prs_shadow_ri_set()
1476 priv->prs_shadow[index].ri = ri; in mvpp2_prs_shadow_ri_set()
1484 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; in mvpp2_prs_tcam_lu_set()
1485 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; in mvpp2_prs_tcam_lu_set()
1488 /* Update mask for single port in tcam sw entry */
1490 unsigned int port, bool add) in mvpp2_prs_tcam_port_set() argument
1495 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1497 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1500 /* Update port map in tcam sw entry */
1507 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; in mvpp2_prs_tcam_port_map_set()
1508 pe->tcam.byte[enable_off] &= ~port_mask; in mvpp2_prs_tcam_port_map_set()
1509 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_set()
1512 /* Obtain port map from tcam sw entry */
1517 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
1525 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; in mvpp2_prs_tcam_data_byte_set()
1526 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; in mvpp2_prs_tcam_data_byte_set()
1534 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; in mvpp2_prs_tcam_data_byte_get()
1535 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; in mvpp2_prs_tcam_data_byte_get()
1550 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); in mvpp2_prs_sram_bits_set()
1557 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); in mvpp2_prs_sram_bits_clear()
1610 bits = (pe->sram.byte[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
1611 (pe->sram.byte[ai_en_off] << (8 - ai_shift)); in mvpp2_prs_sram_ai_get()
1616 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1638 shift = 0 - shift; in mvpp2_prs_sram_shift_set()
1644 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = in mvpp2_prs_sram_shift_set()
1666 offset = 0 - offset; in mvpp2_prs_sram_offset_set()
1675 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1677 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1678 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1680 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1692 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1695 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1697 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1699 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1717 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) { in mvpp2_prs_flow_find()
1720 if (!priv->prs_shadow[tid].valid || in mvpp2_prs_flow_find()
1721 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) in mvpp2_prs_flow_find()
1724 pe->index = tid; in mvpp2_prs_flow_find()
1728 /* Sram store classification lookup ID in AI bits [5:0] */ in mvpp2_prs_flow_find()
1747 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1; in mvpp2_prs_tcam_first_free()
1750 if (!priv->prs_shadow[tid].valid) in mvpp2_prs_tcam_first_free()
1754 return -EINVAL; in mvpp2_prs_tcam_first_free()
1758 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_drop_all_set() argument
1762 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) { in mvpp2_prs_mac_drop_all_set()
1763 /* Entry exist - update port only */ in mvpp2_prs_mac_drop_all_set()
1767 /* Entry doesn't exist - create new */ in mvpp2_prs_mac_drop_all_set()
1772 /* Non-promiscuous mode for all ports - DROP unknown packets */ in mvpp2_prs_mac_drop_all_set()
1786 /* Update port mask */ in mvpp2_prs_mac_drop_all_set()
1787 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1792 /* Set port to promiscuous mode */
1793 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_promisc_set() argument
1797 /* Promiscuous mode - Accept unknown packets */ in mvpp2_prs_mac_promisc_set()
1799 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) { in mvpp2_prs_mac_promisc_set()
1800 /* Entry exist - update port only */ in mvpp2_prs_mac_promisc_set()
1804 /* Entry doesn't exist - create new */ in mvpp2_prs_mac_promisc_set()
1809 /* Continue - set next lookup */ in mvpp2_prs_mac_promisc_set()
1827 /* Update port mask */ in mvpp2_prs_mac_promisc_set()
1828 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1834 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, in mvpp2_prs_mac_multi_set() argument
1845 if (priv->prs_shadow[index].valid) { in mvpp2_prs_mac_multi_set()
1846 /* Entry exist - update port only */ in mvpp2_prs_mac_multi_set()
1850 /* Entry doesn't exist - create new */ in mvpp2_prs_mac_multi_set()
1855 /* Continue - set next lookup */ in mvpp2_prs_mac_multi_set()
1876 /* Update port mask */ in mvpp2_prs_mac_multi_set()
1877 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1882 /* Parser per-port initialization */
1883 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, in mvpp2_prs_hw_port_init() argument
1888 /* Set lookup ID */ in mvpp2_prs_hw_port_init()
1890 val &= ~MVPP2_PRS_PORT_LU_MASK(port); in mvpp2_prs_hw_port_init()
1891 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); in mvpp2_prs_hw_port_init()
1894 /* Set maximum number of loops for packet received from port */ in mvpp2_prs_hw_port_init()
1895 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); in mvpp2_prs_hw_port_init()
1896 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); in mvpp2_prs_hw_port_init()
1897 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); in mvpp2_prs_hw_port_init()
1898 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
1903 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); in mvpp2_prs_hw_port_init()
1904 val &= ~MVPP2_PRS_INIT_OFF_MASK(port); in mvpp2_prs_hw_port_init()
1905 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); in mvpp2_prs_hw_port_init()
1906 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); in mvpp2_prs_hw_port_init()
1913 int port; in mvpp2_prs_def_flow_init() local
1915 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_prs_def_flow_init()
1918 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1923 /* Set flow ID*/ in mvpp2_prs_def_flow_init()
1924 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1954 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1963 /* Non-promiscuous mode for all ports - DROP unknown packets */ in mvpp2_prs_mac_init()
1979 /* place holders only - no ports */ in mvpp2_prs_mac_init()
2012 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2013 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2042 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2043 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2074 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2075 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2111 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2112 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2141 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2142 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2172 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2173 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2178 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */ in mvpp2_prs_etype_init()
2198 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2199 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2231 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE, in mvpp2_prs_default_init()
2234 if (!priv->prs_shadow) in mvpp2_prs_default_init()
2235 return -ENOMEM; in mvpp2_prs_default_init()
2274 /* Find tcam entry with matched pair <MAC DA, port> */
2292 if (!priv->prs_shadow[tid].valid || in mvpp2_prs_mac_da_range_find()
2293 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || in mvpp2_prs_mac_da_range_find()
2294 (priv->prs_shadow[tid].udf != udf_type)) in mvpp2_prs_mac_da_range_find()
2297 pe->index = tid; in mvpp2_prs_mac_da_range_find()
2311 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, in mvpp2_prs_mac_da_accept() argument
2319 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */ in mvpp2_prs_mac_da_accept()
2320 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
2332 if (priv->prs_shadow[tid].valid && in mvpp2_prs_mac_da_accept()
2333 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) && in mvpp2_prs_mac_da_accept()
2334 (priv->prs_shadow[tid].udf == in mvpp2_prs_mac_da_accept()
2340 tid - 1); in mvpp2_prs_mac_da_accept()
2346 return -1; in mvpp2_prs_mac_da_accept()
2348 pe->index = tid; in mvpp2_prs_mac_da_accept()
2354 /* Update port mask */ in mvpp2_prs_mac_da_accept()
2355 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
2362 return -1; in mvpp2_prs_mac_da_accept()
2364 mvpp2_prs_hw_inv(priv, pe->index); in mvpp2_prs_mac_da_accept()
2365 priv->prs_shadow[pe->index].valid = false; in mvpp2_prs_mac_da_accept()
2370 /* Continue - set next lookup */ in mvpp2_prs_mac_da_accept()
2375 while (len--) in mvpp2_prs_mac_da_accept()
2383 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2391 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2392 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2400 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da) in mvpp2_prs_update_mac_da() argument
2405 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr, in mvpp2_prs_update_mac_da()
2411 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); in mvpp2_prs_update_mac_da()
2416 memcpy(port->dev_addr, da, ETH_ALEN); in mvpp2_prs_update_mac_da()
2421 /* Set prs flow for the port */
2422 static int mvpp2_prs_def_flow(struct mvpp2_port *port) in mvpp2_prs_def_flow() argument
2427 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
2432 tid = mvpp2_prs_tcam_first_free(port->priv, in mvpp2_prs_def_flow()
2440 return -ENOMEM; in mvpp2_prs_def_flow()
2443 pe->index = tid; in mvpp2_prs_def_flow()
2445 /* Set flow ID*/ in mvpp2_prs_def_flow()
2446 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2450 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2453 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
2454 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
2466 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); in mvpp2_cls_flow_write()
2467 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); in mvpp2_cls_flow_write()
2468 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); in mvpp2_cls_flow_write()
2469 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); in mvpp2_cls_flow_write()
2478 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; in mvpp2_cls_lookup_write()
2480 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); in mvpp2_cls_lookup_write()
2512 static void mvpp2_cls_port_config(struct mvpp2_port *port) in mvpp2_cls_port_config() argument
2517 /* Set way for the port */ in mvpp2_cls_port_config()
2518 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); in mvpp2_cls_port_config()
2519 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); in mvpp2_cls_port_config()
2520 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); in mvpp2_cls_port_config()
2522 /* Pick the entry to be accessed in lookup ID decoding table in mvpp2_cls_port_config()
2525 le.lkpid = port->id; in mvpp2_cls_port_config()
2531 le.data |= port->first_rxq; in mvpp2_cls_port_config()
2536 /* Update lookup ID table entry */ in mvpp2_cls_port_config()
2537 mvpp2_cls_lookup_write(port->priv, &le); in mvpp2_cls_port_config()
2541 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) in mvpp2_cls_oversize_rxq_set() argument
2545 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2546 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); in mvpp2_cls_oversize_rxq_set()
2548 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2549 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); in mvpp2_cls_oversize_rxq_set()
2551 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set()
2552 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); in mvpp2_cls_oversize_rxq_set()
2553 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
2569 return -EINVAL; in mvpp2_bm_pool_create()
2571 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id]; in mvpp2_bm_pool_create()
2572 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id]; in mvpp2_bm_pool_create()
2573 if (!bm_pool->virt_addr) in mvpp2_bm_pool_create()
2574 return -ENOMEM; in mvpp2_bm_pool_create()
2576 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, in mvpp2_bm_pool_create()
2578 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", in mvpp2_bm_pool_create()
2579 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); in mvpp2_bm_pool_create()
2580 return -ENOMEM; in mvpp2_bm_pool_create()
2583 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
2584 lower_32_bits(bm_pool->dma_addr)); in mvpp2_bm_pool_create()
2585 if (priv->hw_version == MVPP22) in mvpp2_bm_pool_create()
2587 (upper_32_bits(bm_pool->dma_addr) & in mvpp2_bm_pool_create()
2589 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
2591 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_create()
2593 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
2595 bm_pool->type = MVPP2_BM_FREE; in mvpp2_bm_pool_create()
2596 bm_pool->size = size; in mvpp2_bm_pool_create()
2597 bm_pool->pkt_size = 0; in mvpp2_bm_pool_create()
2598 bm_pool->buf_num = 0; in mvpp2_bm_pool_create()
2610 bm_pool->buf_size = buf_size; in mvpp2_bm_pool_bufsize_set()
2613 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
2622 for (i = 0; i < bm_pool->buf_num; i++) { in mvpp2_bm_bufs_free()
2624 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); in mvpp2_bm_bufs_free()
2627 bm_pool->buf_num = 0; in mvpp2_bm_bufs_free()
2638 if (bm_pool->buf_num) { in mvpp2_bm_pool_destroy()
2639 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id); in mvpp2_bm_pool_destroy()
2643 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_destroy()
2645 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
2659 bm_pool = &priv->bm_pools[i]; in mvpp2_bm_pools_init()
2660 bm_pool->id = i; in mvpp2_bm_pools_init()
2669 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); in mvpp2_bm_pools_init()
2670 for (i = i - 1; i >= 0; i--) in mvpp2_bm_pools_init()
2671 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); in mvpp2_bm_pools_init()
2687 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM, in mvpp2_bm_init()
2689 if (!priv->bm_pools) in mvpp2_bm_init()
2690 return -ENOMEM; in mvpp2_bm_init()
2699 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
2705 /* Get queue physical ID */ in mvpp2_rxq_long_pool_set()
2706 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
2708 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_long_pool_set()
2713 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
2716 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
2737 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
2741 if (port->priv->hw_version == MVPP22) { in mvpp2_bm_pool_put()
2753 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val); in mvpp2_bm_pool_put()
2761 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); in mvpp2_bm_pool_put()
2762 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); in mvpp2_bm_pool_put()
2766 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, in mvpp2_pool_refill() argument
2772 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_pool_refill()
2776 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
2782 (buf_num + bm_pool->buf_num > bm_pool->size)) { in mvpp2_bm_bufs_add()
2783 netdev_err(port->dev, in mvpp2_bm_bufs_add()
2785 buf_num, bm_pool->id); in mvpp2_bm_bufs_add()
2790 mvpp2_bm_pool_put(port, bm_pool->id, in mvpp2_bm_bufs_add()
2797 bm_pool->buf_num += i; in mvpp2_bm_bufs_add()
2806 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, in mvpp2_bm_pool_use() argument
2809 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
2812 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) { in mvpp2_bm_pool_use()
2813 netdev_err(port->dev, "mixing pool types is forbidden\n"); in mvpp2_bm_pool_use()
2817 if (new_pool->type == MVPP2_BM_FREE) in mvpp2_bm_pool_use()
2818 new_pool->type = type; in mvpp2_bm_pool_use()
2823 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) || in mvpp2_bm_pool_use()
2824 (new_pool->pkt_size == 0)) { in mvpp2_bm_pool_use()
2830 pkts_num = new_pool->buf_num; in mvpp2_bm_pool_use()
2837 port->priv, new_pool); in mvpp2_bm_pool_use()
2839 new_pool->pkt_size = pkt_size; in mvpp2_bm_pool_use()
2842 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
2845 new_pool->id, num, pkts_num); in mvpp2_bm_pool_use()
2854 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
2858 if (!port->pool_long) { in mvpp2_swf_bm_pool_init()
2859 port->pool_long = in mvpp2_swf_bm_pool_init()
2860 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), in mvpp2_swf_bm_pool_init()
2862 port->pkt_size); in mvpp2_swf_bm_pool_init()
2863 if (!port->pool_long) in mvpp2_swf_bm_pool_init()
2864 return -ENOMEM; in mvpp2_swf_bm_pool_init()
2866 port->pool_long->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
2869 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init()
2875 /* Port configuration routines */
2877 static void mvpp2_port_mii_set(struct mvpp2_port *port) in mvpp2_port_mii_set() argument
2881 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2883 switch (port->phy_interface) { in mvpp2_port_mii_set()
2894 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2897 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) in mvpp2_port_fc_adv_enable() argument
2901 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2903 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2906 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
2910 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2913 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2916 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
2920 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2922 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2926 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
2930 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
2932 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
2935 /* Configure loopback port */
2936 static void mvpp2_port_loopback_set(struct mvpp2_port *port) in mvpp2_port_loopback_set() argument
2940 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2942 if (port->speed == 1000) in mvpp2_port_loopback_set()
2947 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_port_loopback_set()
2952 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2955 static void mvpp2_port_reset(struct mvpp2_port *port) in mvpp2_port_reset() argument
2959 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2961 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_reset()
2963 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2968 /* Change maximum receive size of the port */
2969 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
2973 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2975 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
2977 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2980 /* PPv2.2 GoP/GMAC config */
2983 static int gop_gmac_reset(struct mvpp2_port *port, int reset) in gop_gmac_reset() argument
2987 /* read - modify - write */ in gop_gmac_reset()
2988 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
2993 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
3001 * Configure port to working with Gig PCS or don't.
3003 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en) in gop_gpcs_mode_cfg() argument
3007 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
3012 /* enable / disable PCS on this port */ in gop_gpcs_mode_cfg()
3013 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
3018 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) in gop_bypass_clk_cfg() argument
3022 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3027 /* enable / disable PCS on this port */ in gop_bypass_clk_cfg()
3028 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3033 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) in gop_gmac_sgmii2_5_cfg() argument
3042 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3045 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3048 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3054 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3056 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3058 * Configure GIG MAC to 1000Base-X mode connected to a fiber in gop_gmac_sgmii2_5_cfg()
3062 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3072 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii2_5_cfg()
3075 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) in gop_gmac_sgmii_cfg() argument
3084 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3087 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3090 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3096 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3098 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3101 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3110 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii_cfg()
3113 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port) in gop_gmac_rgmii_cfg() argument
3122 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3125 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3128 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3134 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3136 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3139 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3147 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_rgmii_cfg()
3150 /* Set the internal mux's to the required MAC in the GOP */
3151 static int gop_gmac_mode_cfg(struct mvpp2_port *port) in gop_gmac_mode_cfg() argument
3156 switch (port->phy_interface) { in gop_gmac_mode_cfg()
3158 if (port->phy_speed == 2500) in gop_gmac_mode_cfg()
3159 gop_gmac_sgmii2_5_cfg(port); in gop_gmac_mode_cfg()
3161 gop_gmac_sgmii_cfg(port); in gop_gmac_mode_cfg()
3166 gop_gmac_rgmii_cfg(port); in gop_gmac_mode_cfg()
3170 return -1; in gop_gmac_mode_cfg()
3173 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */ in gop_gmac_mode_cfg()
3174 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3177 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3180 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3182 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3187 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port) in gop_xlg_2_gig_mac_cfg() argument
3192 if (port->gop_id > 0) in gop_xlg_2_gig_mac_cfg()
3196 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3199 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3202 static int gop_gpcs_reset(struct mvpp2_port *port, int reset) in gop_gpcs_reset() argument
3206 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3211 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3217 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes) in gop_xpcs_mode() argument
3233 return -1; in gop_xpcs_mode()
3237 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3241 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3246 static int gop_mpcs_mode(struct mvpp2_port *port) in gop_mpcs_mode() argument
3251 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3253 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3256 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3259 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3265 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3270 /* Set the internal mux's to the required MAC in the GOP */
3271 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes) in gop_xlg_mac_mode_cfg() argument
3276 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3278 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3280 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3283 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3285 /* read - modify - write */ in gop_xlg_mac_mode_cfg()
3286 val = readl(port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3291 writel(val, port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3294 val = readl(port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3297 writel(val, port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3300 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3303 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3309 static int gop_xpcs_reset(struct mvpp2_port *port, int reset) in gop_xpcs_reset() argument
3313 /* read - modify - write */ in gop_xpcs_reset()
3314 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3319 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3325 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset) in gop_xlg_mac_reset() argument
3329 /* read - modify - write */ in gop_xlg_mac_reset()
3330 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3335 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3343 * Init physical port. Configures the port mode and all it's elements
3345 * Does not verify that the selected mode/port number is valid at the
3348 static int gop_port_init(struct mvpp2_port *port) in gop_port_init() argument
3350 int mac_num = port->gop_id; in gop_port_init()
3354 netdev_err(NULL, "%s: illegal port number %d", __func__, in gop_port_init()
3356 return -1; in gop_port_init()
3359 switch (port->phy_interface) { in gop_port_init()
3362 gop_gmac_reset(port, 1); in gop_port_init()
3365 gop_gpcs_mode_cfg(port, 0); in gop_port_init()
3366 gop_bypass_clk_cfg(port, 1); in gop_port_init()
3369 gop_gmac_mode_cfg(port); in gop_port_init()
3371 gop_gpcs_reset(port, 0); in gop_port_init()
3374 gop_gmac_reset(port, 0); in gop_port_init()
3379 gop_gpcs_mode_cfg(port, 1); in gop_port_init()
3382 gop_gmac_mode_cfg(port); in gop_port_init()
3384 gop_xlg_2_gig_mac_cfg(port); in gop_port_init()
3387 gop_gpcs_reset(port, 0); in gop_port_init()
3389 gop_gmac_reset(port, 0); in gop_port_init()
3396 gop_xpcs_mode(port, num_of_act_lanes); in gop_port_init()
3397 gop_mpcs_mode(port); in gop_port_init()
3399 gop_xlg_mac_mode_cfg(port, num_of_act_lanes); in gop_port_init()
3402 gop_xpcs_reset(port, 0); in gop_port_init()
3405 gop_xlg_mac_reset(port, 0); in gop_port_init()
3409 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n", in gop_port_init()
3410 __func__, port->phy_interface); in gop_port_init()
3411 return -1; in gop_port_init()
3417 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable) in gop_xlg_mac_port_enable() argument
3421 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3423 /* Enable port and MIB counters update */ in gop_xlg_mac_port_enable()
3427 /* Disable port */ in gop_xlg_mac_port_enable()
3430 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3433 static void gop_port_enable(struct mvpp2_port *port, int enable) in gop_port_enable() argument
3435 switch (port->phy_interface) { in gop_port_enable()
3440 mvpp2_port_enable(port); in gop_port_enable()
3442 mvpp2_port_disable(port); in gop_port_enable()
3446 gop_xlg_mac_port_enable(port, enable); in gop_port_enable()
3450 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__, in gop_port_enable()
3451 port->phy_interface); in gop_port_enable()
3459 return readl(priv->rfu1_base + offset); in gop_rfu1_read()
3464 writel(data, priv->rfu1_base + offset); in gop_rfu1_write()
3627 /* De-assert the relevant port HB reset */ in gop_netc_mac_to_xgmii()
3653 /* De-assert the relevant port HB reset */ in gop_netc_mac_to_sgmii()
3661 u32 c = priv->netc_config; in gop_netc_init()
3678 /* Activate gop ports 0, 2, 3 */ in gop_netc_init()
3684 /* Enable the GOP internal clock logic */ in gop_netc_init()
3686 /* De-assert GOP unit reset */ in gop_netc_init()
3693 /* Set defaults to the MVPP2 port */
3694 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
3698 if (port->priv->hw_version == MVPP21) { in mvpp2_defaults_set()
3699 /* Configure port to loopback if needed */ in mvpp2_defaults_set()
3700 if (port->flags & MVPP2_F_LOOPBACK) in mvpp2_defaults_set()
3701 mvpp2_port_loopback_set(port); in mvpp2_defaults_set()
3704 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3707 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); in mvpp2_defaults_set()
3708 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3712 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
3713 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
3715 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
3719 ptxq = mvpp2_txq_phys(port->id, queue); in mvpp2_defaults_set()
3720 mvpp2_write(port->priv, in mvpp2_defaults_set()
3727 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8); in mvpp2_defaults_set()
3728 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
3732 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
3734 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
3737 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
3743 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
3744 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
3747 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3752 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
3758 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
3759 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
3761 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
3765 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
3771 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
3772 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
3774 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
3779 * - HW starts take descriptors from DRAM
3781 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
3785 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
3790 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
3792 if (txq->descs != NULL) in mvpp2_egress_enable()
3796 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
3797 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
3801 * - HW doesn't take descriptors from DRAM
3803 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
3807 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
3810 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
3811 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
3814 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
3821 netdev_warn(port->dev, in mvpp2_egress_disable()
3829 /* Check port TX Command register that all in mvpp2_egress_disable()
3832 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
3840 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
3842 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
3851 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
3859 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
3866 int rx_desc = rxq->next_desc_to_proc; in mvpp2_rxq_next_desc_get()
3868 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); in mvpp2_rxq_next_desc_get()
3869 prefetch(rxq->descs + rxq->next_desc_to_proc); in mvpp2_rxq_next_desc_get()
3870 return rxq->descs + rx_desc; in mvpp2_rxq_next_desc_get()
3874 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
3882 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
3889 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
3893 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port, in mvpp2_bm_cookie_build() argument
3899 pool = (mvpp2_rxdesc_status_get(port, rx_desc) & in mvpp2_bm_cookie_build()
3910 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port, in mvpp2_txq_pend_desc_num_get() argument
3915 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_pend_desc_num_get()
3916 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_pend_desc_num_get()
3925 int tx_desc = txq->next_desc_to_proc; in mvpp2_txq_next_desc_get()
3927 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); in mvpp2_txq_next_desc_get()
3928 return txq->descs + tx_desc; in mvpp2_txq_next_desc_get()
3932 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
3934 /* aggregated access - relevant TXQ number is written in TX desc */ in mvpp2_aggr_txq_pend_desc_add()
3935 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); in mvpp2_aggr_txq_pend_desc_add()
3940 * Per-CPU access
3942 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
3948 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id)); in mvpp2_txq_sent_desc_proc()
3956 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
3960 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear() local
3962 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id)); in mvpp2_txq_sent_counter_clear()
3967 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
3972 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
3980 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
3981 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
3984 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
3987 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
3990 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
3996 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
4000 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
4008 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
4016 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
4026 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
4029 int queue = fls(cause) - 1; in mvpp2_get_rx_queue()
4031 return port->rxqs[queue]; in mvpp2_get_rx_queue()
4034 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
4037 int queue = fls(cause) - 1; in mvpp2_get_tx_queue()
4039 return port->txqs[queue]; in mvpp2_get_tx_queue()
4053 aggr_txq->descs = buffer_loc.aggr_tx_descs; in mvpp2_aggr_txq_init()
4054 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs; in mvpp2_aggr_txq_init()
4055 if (!aggr_txq->descs) in mvpp2_aggr_txq_init()
4056 return -ENOMEM; in mvpp2_aggr_txq_init()
4059 BUG_ON(aggr_txq->descs != in mvpp2_aggr_txq_init()
4060 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); in mvpp2_aggr_txq_init()
4062 aggr_txq->last_desc = aggr_txq->size - 1; in mvpp2_aggr_txq_init()
4065 aggr_txq->next_desc_to_proc = mvpp2_read(priv, in mvpp2_aggr_txq_init()
4071 if (priv->hw_version == MVPP21) in mvpp2_aggr_txq_init()
4072 txq_dma = aggr_txq->descs_dma; in mvpp2_aggr_txq_init()
4074 txq_dma = aggr_txq->descs_dma >> in mvpp2_aggr_txq_init()
4084 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
4090 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
4093 rxq->descs = buffer_loc.rx_descs; in mvpp2_rxq_init()
4094 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs; in mvpp2_rxq_init()
4095 if (!rxq->descs) in mvpp2_rxq_init()
4096 return -ENOMEM; in mvpp2_rxq_init()
4098 BUG_ON(rxq->descs != in mvpp2_rxq_init()
4099 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); in mvpp2_rxq_init()
4101 rxq->last_desc = rxq->size - 1; in mvpp2_rxq_init()
4103 /* Zero occupied and non-occupied counters - direct access */ in mvpp2_rxq_init()
4104 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
4106 /* Set Rx descriptors queue starting address - indirect access */ in mvpp2_rxq_init()
4107 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
4108 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_init()
4109 rxq_dma = rxq->descs_dma; in mvpp2_rxq_init()
4111 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; in mvpp2_rxq_init()
4112 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
4113 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
4114 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
4117 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); in mvpp2_rxq_init()
4120 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
4126 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
4131 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
4137 u32 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_rxq_drop_pkts()
4139 mvpp2_pool_refill(port, bm, in mvpp2_rxq_drop_pkts()
4140 mvpp2_rxdesc_dma_addr_get(port, rx_desc), in mvpp2_rxq_drop_pkts()
4141 mvpp2_rxdesc_cookie_get(port, rx_desc)); in mvpp2_rxq_drop_pkts()
4143 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
4147 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
4150 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
4152 rxq->descs = NULL; in mvpp2_rxq_deinit()
4153 rxq->last_desc = 0; in mvpp2_rxq_deinit()
4154 rxq->next_desc_to_proc = 0; in mvpp2_rxq_deinit()
4155 rxq->descs_dma = 0; in mvpp2_rxq_deinit()
4160 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
4161 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
4162 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
4163 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
4167 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
4174 txq->size = port->tx_ring_size; in mvpp2_txq_init()
4177 txq->descs = buffer_loc.tx_descs; in mvpp2_txq_init()
4178 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs; in mvpp2_txq_init()
4179 if (!txq->descs) in mvpp2_txq_init()
4180 return -ENOMEM; in mvpp2_txq_init()
4183 BUG_ON(txq->descs != in mvpp2_txq_init()
4184 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); in mvpp2_txq_init()
4186 txq->last_desc = txq->size - 1; in mvpp2_txq_init()
4188 /* Set Tx descriptors queue starting address - indirect access */ in mvpp2_txq_init()
4189 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
4190 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma); in mvpp2_txq_init()
4191 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & in mvpp2_txq_init()
4193 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
4194 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
4195 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); in mvpp2_txq_init()
4196 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
4198 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
4202 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT in mvpp2_txq_init()
4206 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
4207 (txq->log_id * desc_per_txq); in mvpp2_txq_init()
4209 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
4213 /* WRR / EJP configuration - indirect access */ in mvpp2_txq_init()
4214 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
4215 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
4217 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
4221 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
4224 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
4228 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); in mvpp2_txq_init()
4229 txq_pcpu->size = txq->size; in mvpp2_txq_init()
4236 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
4239 txq->descs = NULL; in mvpp2_txq_deinit()
4240 txq->last_desc = 0; in mvpp2_txq_deinit()
4241 txq->next_desc_to_proc = 0; in mvpp2_txq_deinit()
4242 txq->descs_dma = 0; in mvpp2_txq_deinit()
4245 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); in mvpp2_txq_deinit()
4248 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
4249 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
4250 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
4254 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
4260 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
4261 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
4263 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4271 netdev_warn(port->dev, in mvpp2_txq_clean()
4272 "port %d: cleaning queue %d timed out\n", in mvpp2_txq_clean()
4273 port->id, txq->log_id); in mvpp2_txq_clean()
4279 pending = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_txq_clean()
4283 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4286 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); in mvpp2_txq_clean()
4289 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
4292 txq_pcpu->count = 0; in mvpp2_txq_clean()
4293 txq_pcpu->txq_put_index = 0; in mvpp2_txq_clean()
4294 txq_pcpu->txq_get_index = 0; in mvpp2_txq_clean()
4299 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
4305 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
4308 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4309 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4312 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
4313 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
4314 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
4317 mvpp2_txq_sent_counter_clear(port); in mvpp2_cleanup_txqs()
4319 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4320 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4324 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
4329 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
4332 /* Init all Rx queues for port */
4333 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
4338 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
4345 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
4349 /* Init all tx queues for port */
4350 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
4356 txq = port->txqs[queue]; in mvpp2_setup_txqs()
4357 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
4362 mvpp2_txq_sent_counter_clear(port); in mvpp2_setup_txqs()
4366 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
4371 static void mvpp2_link_event(struct mvpp2_port *port) in mvpp2_link_event() argument
4373 struct phy_device *phydev = port->phy_dev; in mvpp2_link_event()
4377 if (phydev->link) { in mvpp2_link_event()
4378 if ((port->speed != phydev->speed) || in mvpp2_link_event()
4379 (port->duplex != phydev->duplex)) { in mvpp2_link_event()
4382 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4389 if (phydev->duplex) in mvpp2_link_event()
4392 if (phydev->speed == SPEED_1000) in mvpp2_link_event()
4394 else if (phydev->speed == SPEED_100) in mvpp2_link_event()
4397 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4399 port->duplex = phydev->duplex; in mvpp2_link_event()
4400 port->speed = phydev->speed; in mvpp2_link_event()
4404 if (phydev->link != port->link) { in mvpp2_link_event()
4405 if (!phydev->link) { in mvpp2_link_event()
4406 port->duplex = -1; in mvpp2_link_event()
4407 port->speed = 0; in mvpp2_link_event()
4410 port->link = phydev->link; in mvpp2_link_event()
4415 if (phydev->link) { in mvpp2_link_event()
4416 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4419 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4420 mvpp2_egress_enable(port); in mvpp2_link_event()
4421 mvpp2_ingress_enable(port); in mvpp2_link_event()
4423 mvpp2_ingress_disable(port); in mvpp2_link_event()
4424 mvpp2_egress_disable(port); in mvpp2_link_event()
4432 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
4435 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx_error()
4436 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx_error()
4440 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", in mvpp2_rx_error()
4444 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", in mvpp2_rx_error()
4448 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", in mvpp2_rx_error()
4455 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
4459 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr); in mvpp2_rx_refill()
4463 /* Set hw internals when starting port */
4464 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
4466 switch (port->phy_interface) { in mvpp2_start_dev()
4470 mvpp2_gmac_max_rx_size_set(port); in mvpp2_start_dev()
4475 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
4477 if (port->priv->hw_version == MVPP21) in mvpp2_start_dev()
4478 mvpp2_port_enable(port); in mvpp2_start_dev()
4480 gop_port_enable(port, 1); in mvpp2_start_dev()
4483 /* Set hw internals when stopping port */
4484 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
4487 mvpp2_ingress_disable(port); in mvpp2_stop_dev()
4489 mvpp2_egress_disable(port); in mvpp2_stop_dev()
4491 if (port->priv->hw_version == MVPP21) in mvpp2_stop_dev()
4492 mvpp2_port_disable(port); in mvpp2_stop_dev()
4494 gop_port_enable(port, 0); in mvpp2_stop_dev()
4497 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) in mvpp2_phy_connect() argument
4501 if (!port->init || port->link == 0) { in mvpp2_phy_connect()
4502 phy_dev = phy_connect(port->bus, port->phyaddr, dev, in mvpp2_phy_connect()
4503 port->phy_interface); in mvpp2_phy_connect()
4504 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4506 netdev_err(port->dev, "cannot connect to phy\n"); in mvpp2_phy_connect()
4507 return -ENODEV; in mvpp2_phy_connect()
4509 phy_dev->supported &= PHY_GBIT_FEATURES; in mvpp2_phy_connect()
4510 phy_dev->advertising = phy_dev->supported; in mvpp2_phy_connect()
4512 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4513 port->link = 0; in mvpp2_phy_connect()
4514 port->duplex = 0; in mvpp2_phy_connect()
4515 port->speed = 0; in mvpp2_phy_connect()
4519 if (!phy_dev->link) { in mvpp2_phy_connect()
4520 printf("%s: No link\n", phy_dev->dev->name); in mvpp2_phy_connect()
4521 return -1; in mvpp2_phy_connect()
4524 port->init = 1; in mvpp2_phy_connect()
4526 mvpp2_egress_enable(port); in mvpp2_phy_connect()
4527 mvpp2_ingress_enable(port); in mvpp2_phy_connect()
4533 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port) in mvpp2_open() argument
4539 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); in mvpp2_open()
4544 err = mvpp2_prs_mac_da_accept(port->priv, port->id, in mvpp2_open()
4545 port->dev_addr, true); in mvpp2_open()
4550 err = mvpp2_prs_def_flow(port); in mvpp2_open()
4557 err = mvpp2_setup_rxqs(port); in mvpp2_open()
4559 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
4563 err = mvpp2_setup_txqs(port); in mvpp2_open()
4565 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
4569 if (port->phy_node) { in mvpp2_open()
4570 err = mvpp2_phy_connect(dev, port); in mvpp2_open()
4574 mvpp2_link_event(port); in mvpp2_open()
4576 mvpp2_egress_enable(port); in mvpp2_open()
4577 mvpp2_ingress_enable(port); in mvpp2_open()
4580 mvpp2_start_dev(port); in mvpp2_open()
4585 /* No Device ops here in U-Boot */
4589 static void mvpp2_port_power_up(struct mvpp2_port *port) in mvpp2_port_power_up() argument
4591 struct mvpp2 *priv = port->priv; in mvpp2_port_power_up()
4593 /* On PPv2.2 the GoP / interface configuration has already been done */ in mvpp2_port_power_up()
4594 if (priv->hw_version == MVPP21) in mvpp2_port_power_up()
4595 mvpp2_port_mii_set(port); in mvpp2_port_power_up()
4596 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_power_up()
4597 if (priv->hw_version == MVPP21) in mvpp2_port_power_up()
4598 mvpp2_port_fc_adv_enable(port); in mvpp2_port_power_up()
4599 mvpp2_port_reset(port); in mvpp2_port_power_up()
4602 /* Initialize port HW */
4603 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) in mvpp2_port_init() argument
4605 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
4609 if (port->first_rxq + rxq_number > in mvpp2_port_init()
4610 MVPP2_MAX_PORTS * priv->max_port_rxqs) in mvpp2_port_init()
4611 return -EINVAL; in mvpp2_port_init()
4613 /* Disable port */ in mvpp2_port_init()
4614 mvpp2_egress_disable(port); in mvpp2_port_init()
4615 if (priv->hw_version == MVPP21) in mvpp2_port_init()
4616 mvpp2_port_disable(port); in mvpp2_port_init()
4618 gop_port_enable(port, 0); in mvpp2_port_init()
4620 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), in mvpp2_port_init()
4622 if (!port->txqs) in mvpp2_port_init()
4623 return -ENOMEM; in mvpp2_port_init()
4625 /* Associate physical Tx queues to this port and initialize. in mvpp2_port_init()
4629 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
4634 return -ENOMEM; in mvpp2_port_init()
4636 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu), in mvpp2_port_init()
4638 if (!txq->pcpu) in mvpp2_port_init()
4639 return -ENOMEM; in mvpp2_port_init()
4641 txq->id = queue_phy_id; in mvpp2_port_init()
4642 txq->log_id = queue; in mvpp2_port_init()
4643 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; in mvpp2_port_init()
4645 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); in mvpp2_port_init()
4646 txq_pcpu->cpu = cpu; in mvpp2_port_init()
4649 port->txqs[queue] = txq; in mvpp2_port_init()
4652 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs), in mvpp2_port_init()
4654 if (!port->rxqs) in mvpp2_port_init()
4655 return -ENOMEM; in mvpp2_port_init()
4657 /* Allocate and initialize Rx queue for this port */ in mvpp2_port_init()
4661 /* Map physical Rx queue to port's logical Rx queue */ in mvpp2_port_init()
4664 return -ENOMEM; in mvpp2_port_init()
4666 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
4667 rxq->port = port->id; in mvpp2_port_init()
4668 rxq->logic_rxq = queue; in mvpp2_port_init()
4670 port->rxqs[queue] = rxq; in mvpp2_port_init()
4676 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
4678 rxq->size = port->rx_ring_size; in mvpp2_port_init()
4679 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; in mvpp2_port_init()
4680 rxq->time_coal = MVPP2_RX_COAL_USEC; in mvpp2_port_init()
4683 mvpp2_ingress_disable(port); in mvpp2_port_init()
4685 /* Port default configuration */ in mvpp2_port_init()
4686 mvpp2_defaults_set(port); in mvpp2_port_init()
4688 /* Port's classifier configuration */ in mvpp2_port_init()
4689 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
4690 mvpp2_cls_port_config(port); in mvpp2_port_init()
4693 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN); in mvpp2_port_init()
4696 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
4703 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) in phy_info_parse() argument
4708 u32 id; in phy_info_parse() local
4710 int phy_mode = -1; in phy_info_parse()
4713 if (port->priv->hw_version == MVPP21) in phy_info_parse()
4714 port->mdio_base = port->priv->lms_base + MVPP21_SMI; in phy_info_parse()
4716 port->mdio_base = port->priv->iface_base + MVPP22_SMI; in phy_info_parse()
4718 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy"); in phy_info_parse()
4724 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0); in phy_info_parse()
4726 dev_err(&pdev->dev, "could not find phy address\n"); in phy_info_parse()
4727 return -1; in phy_info_parse()
4732 port->mdio_base = (void *)phy_base; in phy_info_parse()
4734 if (port->mdio_base < 0) { in phy_info_parse()
4735 dev_err(&pdev->dev, "could not find mdio base address\n"); in phy_info_parse()
4736 return -1; in phy_info_parse()
4742 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL); in phy_info_parse()
4745 if (phy_mode == -1) { in phy_info_parse()
4746 dev_err(&pdev->dev, "incorrect phy mode\n"); in phy_info_parse()
4747 return -EINVAL; in phy_info_parse()
4750 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1); in phy_info_parse()
4751 if (id == -1) { in phy_info_parse()
4752 dev_err(&pdev->dev, "missing port-id value\n"); in phy_info_parse()
4753 return -EINVAL; in phy_info_parse()
4757 gpio_request_by_name(dev, "phy-reset-gpios", 0, in phy_info_parse()
4758 &port->phy_reset_gpio, GPIOD_IS_OUT); in phy_info_parse()
4759 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0, in phy_info_parse()
4760 &port->phy_tx_disable_gpio, GPIOD_IS_OUT); in phy_info_parse()
4765 * Not sure if this DT property "phy-speed" will get accepted, so in phy_info_parse()
4768 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */ in phy_info_parse()
4769 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node, in phy_info_parse()
4770 "phy-speed", 1000); in phy_info_parse()
4772 port->id = id; in phy_info_parse()
4773 if (port->priv->hw_version == MVPP21) in phy_info_parse()
4774 port->first_rxq = port->id * rxq_number; in phy_info_parse()
4776 port->first_rxq = port->id * port->priv->max_port_rxqs; in phy_info_parse()
4777 port->phy_node = phy_node; in phy_info_parse()
4778 port->phy_interface = phy_mode; in phy_info_parse()
4779 port->phyaddr = phyaddr; in phy_info_parse()
4785 /* Port GPIO initialization */
4786 static void mvpp2_gpio_init(struct mvpp2_port *port) in mvpp2_gpio_init() argument
4788 if (dm_gpio_is_valid(&port->phy_reset_gpio)) { in mvpp2_gpio_init()
4789 dm_gpio_set_value(&port->phy_reset_gpio, 1); in mvpp2_gpio_init()
4791 dm_gpio_set_value(&port->phy_reset_gpio, 0); in mvpp2_gpio_init()
4794 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio)) in mvpp2_gpio_init()
4795 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0); in mvpp2_gpio_init()
4801 struct mvpp2_port *port, in mvpp2_port_probe() argument
4807 port->tx_ring_size = MVPP2_MAX_TXD; in mvpp2_port_probe()
4808 port->rx_ring_size = MVPP2_MAX_RXD; in mvpp2_port_probe()
4810 err = mvpp2_port_init(dev, port); in mvpp2_port_probe()
4812 dev_err(&pdev->dev, "failed to init port %d\n", port->id); in mvpp2_port_probe()
4815 mvpp2_port_power_up(port); in mvpp2_port_probe()
4818 mvpp2_gpio_init(port); in mvpp2_port_probe()
4821 priv->port_list[port->id] = port; in mvpp2_port_probe()
4822 priv->num_ports++; in mvpp2_port_probe()
4843 for (i = 0; i < dram->num_cs; i++) { in mvpp2_conf_mbus_windows()
4844 const struct mbus_dram_window *cs = dram->cs + i; in mvpp2_conf_mbus_windows()
4847 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | in mvpp2_conf_mbus_windows()
4848 dram->mbus_dram_target_id); in mvpp2_conf_mbus_windows()
4851 (cs->size - 1) & 0xffff0000); in mvpp2_conf_mbus_windows()
4862 int port; in mvpp2_rx_fifo_init() local
4864 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
4865 if (priv->hw_version == MVPP22) { in mvpp2_rx_fifo_init()
4866 if (port == 0) { in mvpp2_rx_fifo_init()
4868 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4871 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4873 } else if (port == 1) { in mvpp2_rx_fifo_init()
4875 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4878 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4882 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4885 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4889 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4891 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4904 int port, val; in mvpp2_tx_fifo_init() local
4906 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_tx_fifo_init()
4907 /* Port 0 supports 10KB TX FIFO */ in mvpp2_tx_fifo_init()
4908 if (port == 0) { in mvpp2_tx_fifo_init()
4915 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
4980 /* Checks for hardware constraints (U-Boot uses only one rxq) */ in mvpp2_init()
4981 if ((rxq_number > priv->max_port_rxqs) || in mvpp2_init()
4983 dev_err(&pdev->dev, "invalid queue size parameter\n"); in mvpp2_init()
4984 return -EINVAL; in mvpp2_init()
4987 if (priv->hw_version == MVPP22) in mvpp2_init()
4996 if (priv->hw_version == MVPP21) { in mvpp2_init()
4998 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); in mvpp2_init()
5000 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); in mvpp2_init()
5003 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); in mvpp2_init()
5005 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); in mvpp2_init()
5009 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(), in mvpp2_init()
5012 if (!priv->aggr_txqs) in mvpp2_init()
5013 return -ENOMEM; in mvpp2_init()
5016 priv->aggr_txqs[i].id = i; in mvpp2_init()
5017 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; in mvpp2_init()
5018 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i], in mvpp2_init()
5028 if (priv->hw_version == MVPP22) in mvpp2_init()
5031 if (priv->hw_version == MVPP21) in mvpp2_init()
5033 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); in mvpp2_init()
5064 smi_reg = readl(priv->mdio_base); in smi_wait_ready()
5065 if (timeout-- == 0) { in smi_wait_ready()
5067 return -EFAULT; in smi_wait_ready()
5075 * mpp2_mdio_read - miiphy_read callback function.
5081 struct mvpp2_port *priv = bus->priv; in mpp2_mdio_read()
5088 return -EFAULT; in mpp2_mdio_read()
5093 return -EFAULT; in mpp2_mdio_read()
5098 return -EFAULT; in mpp2_mdio_read()
5106 writel(smi_reg, priv->mdio_base); in mpp2_mdio_read()
5113 smi_reg = readl(priv->mdio_base); in mpp2_mdio_read()
5114 if (timeout-- == 0) { in mpp2_mdio_read()
5116 return -EFAULT; in mpp2_mdio_read()
5124 return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK; in mpp2_mdio_read()
5128 * mpp2_mdio_write - miiphy_write callback function.
5130 * Returns 0 if write succeed, -EINVAL on bad parameters
5131 * -ETIME on timeout
5136 struct mvpp2_port *priv = bus->priv; in mpp2_mdio_write()
5142 return -EFAULT; in mpp2_mdio_write()
5147 return -EFAULT; in mpp2_mdio_write()
5152 return -EFAULT; in mpp2_mdio_write()
5161 writel(smi_reg, priv->mdio_base); in mpp2_mdio_write()
5168 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_recv() local
5179 rxq = port->rxqs[0]; in mvpp2_recv()
5181 /* Get number of received packets and clamp the to-do */ in mvpp2_recv()
5182 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_recv()
5189 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_recv()
5190 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_recv()
5191 rx_bytes -= MVPP2_MH_SIZE; in mvpp2_recv()
5192 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_recv()
5194 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_recv()
5196 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_recv()
5204 mvpp2_rx_error(port, rx_desc); in mvpp2_recv()
5206 mvpp2_pool_refill(port, bm, dma_addr, dma_addr); in mvpp2_recv()
5210 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr); in mvpp2_recv()
5212 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_recv()
5218 mvpp2_rxq_status_update(port, rxq->id, 1, 1); in mvpp2_recv()
5220 /* give packet to stack - skip on first n bytes */ in mvpp2_recv()
5237 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_send() local
5243 txq = port->txqs[0]; in mvpp2_send()
5244 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; in mvpp2_send()
5248 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_send()
5249 mvpp2_txdesc_size_set(port, tx_desc, length); in mvpp2_send()
5250 mvpp2_txdesc_offset_set(port, tx_desc, in mvpp2_send()
5252 mvpp2_txdesc_dma_addr_set(port, tx_desc, in mvpp2_send()
5255 mvpp2_txdesc_cmd_set(port, tx_desc, in mvpp2_send()
5265 mvpp2_aggr_txq_pend_desc_add(port, 1); in mvpp2_send()
5267 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_send()
5275 tx_done = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_send()
5284 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_send()
5293 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_start() local
5296 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN); in mvpp2_start()
5299 mvpp2_prs_update_mac_da(port, port->dev_addr); in mvpp2_start()
5301 switch (port->phy_interface) { in mvpp2_start()
5305 mvpp2_port_power_up(port); in mvpp2_start()
5310 mvpp2_open(dev, port); in mvpp2_start()
5317 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_stop() local
5319 mvpp2_stop_dev(port); in mvpp2_stop()
5320 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
5321 mvpp2_cleanup_txqs(port); in mvpp2_stop()
5324 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) in mvpp22_smi_phy_addr_cfg() argument
5326 writel(port->phyaddr, port->priv->iface_base + in mvpp22_smi_phy_addr_cfg()
5327 MVPP22_SMI_PHY_ADDR_REG(port->gop_id)); in mvpp22_smi_phy_addr_cfg()
5339 /* Save hw-version */ in mvpp2_base_probe()
5340 priv->hw_version = dev_get_driver_data(dev); in mvpp2_base_probe()
5343 * U-Boot special buffer handling: in mvpp2_base_probe()
5347 * be active. Make this area DMA-safe by disabling the D-cache in mvpp2_base_probe()
5369 if (priv->hw_version == MVPP21) in mvpp2_base_probe()
5385 priv->base = (void *)devfdt_get_addr_index(dev, 0); in mvpp2_base_probe()
5386 if (IS_ERR(priv->base)) in mvpp2_base_probe()
5387 return PTR_ERR(priv->base); in mvpp2_base_probe()
5389 if (priv->hw_version == MVPP21) { in mvpp2_base_probe()
5390 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1); in mvpp2_base_probe()
5391 if (IS_ERR(priv->lms_base)) in mvpp2_base_probe()
5392 return PTR_ERR(priv->lms_base); in mvpp2_base_probe()
5394 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1); in mvpp2_base_probe()
5395 if (IS_ERR(priv->iface_base)) in mvpp2_base_probe()
5396 return PTR_ERR(priv->iface_base); in mvpp2_base_probe()
5399 priv->mpcs_base = priv->iface_base + MVPP22_MPCS; in mvpp2_base_probe()
5400 priv->xpcs_base = priv->iface_base + MVPP22_XPCS; in mvpp2_base_probe()
5401 priv->rfu1_base = priv->iface_base + MVPP22_RFU1; in mvpp2_base_probe()
5404 if (priv->hw_version == MVPP21) in mvpp2_base_probe()
5405 priv->max_port_rxqs = 8; in mvpp2_base_probe()
5407 priv->max_port_rxqs = 32; in mvpp2_base_probe()
5414 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_probe() local
5415 struct mvpp2 *priv = dev_get_priv(dev->parent); in mvpp2_probe()
5420 if (!priv->probe_done) in mvpp2_probe()
5421 err = mvpp2_base_probe(dev->parent); in mvpp2_probe()
5423 port->priv = dev_get_priv(dev->parent); in mvpp2_probe()
5429 return -ENOMEM; in mvpp2_probe()
5432 bus->read = mpp2_mdio_read; in mvpp2_probe()
5433 bus->write = mpp2_mdio_write; in mvpp2_probe()
5434 snprintf(bus->name, sizeof(bus->name), dev->name); in mvpp2_probe()
5435 bus->priv = (void *)port; in mvpp2_probe()
5436 port->bus = bus; in mvpp2_probe()
5442 err = phy_info_parse(dev, port); in mvpp2_probe()
5447 * We need the port specific io base addresses at this stage, since in mvpp2_probe()
5450 if (priv->hw_version == MVPP21) { in mvpp2_probe()
5453 port->base = (void __iomem *)devfdt_get_addr_index( in mvpp2_probe()
5454 dev->parent, priv_common_regs_num + port->id); in mvpp2_probe()
5455 if (IS_ERR(port->base)) in mvpp2_probe()
5456 return PTR_ERR(port->base); in mvpp2_probe()
5458 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in mvpp2_probe()
5459 "gop-port-id", -1); in mvpp2_probe()
5460 if (port->id == -1) { in mvpp2_probe()
5461 dev_err(&pdev->dev, "missing gop-port-id value\n"); in mvpp2_probe()
5462 return -EINVAL; in mvpp2_probe()
5465 port->base = priv->iface_base + MVPP22_PORT_BASE + in mvpp2_probe()
5466 port->gop_id * MVPP22_PORT_OFFSET; in mvpp2_probe()
5468 /* Set phy address of the port */ in mvpp2_probe()
5469 if(port->phy_node) in mvpp2_probe()
5470 mvpp22_smi_phy_addr_cfg(port); in mvpp2_probe()
5472 /* GoP Init */ in mvpp2_probe()
5473 gop_port_init(port); in mvpp2_probe()
5476 if (!priv->probe_done) { in mvpp2_probe()
5480 dev_err(&pdev->dev, "failed to initialize controller\n"); in mvpp2_probe()
5483 priv->num_ports = 0; in mvpp2_probe()
5484 priv->probe_done = 1; in mvpp2_probe()
5487 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); in mvpp2_probe()
5491 if (priv->hw_version == MVPP22) { in mvpp2_probe()
5492 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id, in mvpp2_probe()
5493 port->phy_interface); in mvpp2_probe()
5508 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_remove() local
5509 struct mvpp2 *priv = port->priv; in mvpp2_remove()
5512 priv->num_ports--; in mvpp2_remove()
5514 if (priv->num_ports) in mvpp2_remove()
5518 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); in mvpp2_remove()
5532 .id = UCLASS_ETH,
5547 const void *blob = gd->fdt_blob; in mvpp2_base_bind()
5554 u32 id; in mvpp2_base_bind() local
5561 return -ENOENT; in mvpp2_base_bind()
5576 return -ENOMEM; in mvpp2_base_bind()
5578 id = fdtdec_get_int(blob, subnode, "port-id", -1); in mvpp2_base_bind()
5579 id += base_id_add; in mvpp2_base_bind()
5584 return -ENOMEM; in mvpp2_base_bind()
5586 sprintf(name, "mvpp2-%d", id); in mvpp2_base_bind()
5598 .compatible = "marvell,armada-375-pp2",
5602 .compatible = "marvell,armada-7k-pp22",
5610 .id = UCLASS_MISC,