199 static int mii_mgr_write(struct mt7628_eth_dev *priv,  in mii_mgr_write()  function
235 	return mii_mgr_write(bus->priv, addr, reg, value);  in mt7628_mdio_write()
242 	mii_mgr_write(priv, 0, 31, 0x2000);	/* change G2 page */  in mt7628_ephy_init()
243 	mii_mgr_write(priv, 0, 26, 0x0000);  in mt7628_ephy_init()
246 		mii_mgr_write(priv, i, 31, 0x8000);	/* change L0 page */  in mt7628_ephy_init()
247 		mii_mgr_write(priv, i,  0, 0x3100);  in mt7628_ephy_init()
250 		mii_mgr_write(priv, i, 30, 0xa000);  in mt7628_ephy_init()
251 		mii_mgr_write(priv, i, 31, 0xa000);	/* change L2 page */  in mt7628_ephy_init()
252 		mii_mgr_write(priv, i, 16, 0x0606);  in mt7628_ephy_init()
253 		mii_mgr_write(priv, i, 23, 0x0f0e);  in mt7628_ephy_init()
254 		mii_mgr_write(priv, i, 24, 0x1610);  in mt7628_ephy_init()
255 		mii_mgr_write(priv, i, 30, 0x1f15);  in mt7628_ephy_init()
256 		mii_mgr_write(priv, i, 28, 0x6111);  in mt7628_ephy_init()
260 	mii_mgr_write(priv, 0, 31, 0x5000);	/* change G5 page */  in mt7628_ephy_init()
261 	mii_mgr_write(priv, 0, 19, 0x004a);  in mt7628_ephy_init()
262 	mii_mgr_write(priv, 0, 20, 0x015a);  in mt7628_ephy_init()
263 	mii_mgr_write(priv, 0, 21, 0x00ee);  in mt7628_ephy_init()
264 	mii_mgr_write(priv, 0, 22, 0x0033);  in mt7628_ephy_init()
265 	mii_mgr_write(priv, 0, 23, 0x020a);  in mt7628_ephy_init()
266 	mii_mgr_write(priv, 0, 24, 0x0000);  in mt7628_ephy_init()
267 	mii_mgr_write(priv, 0, 25, 0x024a);  in mt7628_ephy_init()
268 	mii_mgr_write(priv, 0, 26, 0x035a);  in mt7628_ephy_init()
269 	mii_mgr_write(priv, 0, 27, 0x02ee);  in mt7628_ephy_init()
270 	mii_mgr_write(priv, 0, 28, 0x0233);  in mt7628_ephy_init()
271 	mii_mgr_write(priv, 0, 29, 0x000a);  in mt7628_ephy_init()
272 	mii_mgr_write(priv, 0, 30, 0x0000);  in mt7628_ephy_init()
275 	mii_mgr_write(priv, 0, 31, 0x4000);	/* change G4 page */  in mt7628_ephy_init()
276 	mii_mgr_write(priv, 0, 29, 0x000d);  in mt7628_ephy_init()
277 	mii_mgr_write(priv, 0, 30, 0x0500);  in mt7628_ephy_init()