1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
110 #define MAX_PORT (PORT3 - PORT0)
113 	MIIM,  enumerator
143 static struct mscc_miim_dev miim[NUM_PHY];  variable
147 	struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;  in mscc_miim_reset()  local
149 	if (miim->phy_regs) {  in mscc_miim_reset()
150 		writel(0, miim->phy_regs + PHY_CFG);  in mscc_miim_reset()
152 		       | PHY_CFG_ENA, miim->phy_regs + PHY_CFG);  in mscc_miim_reset()
179 	ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,  in ocelot_mdiobus_init()
190 		phy_size[i] = res.end - res.start;  in ocelot_mdiobus_init()
193 	strcpy(bus->name, "miim-internal");  in ocelot_mdiobus_init()
194 	miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);  in ocelot_mdiobus_init()
195 	miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);  in ocelot_mdiobus_init()
196 	bus->priv = &miim[INTERNAL];  in ocelot_mdiobus_init()
197 	bus->reset = mscc_miim_reset;  in ocelot_mdiobus_init()
198 	bus->read = mscc_miim_read;  in ocelot_mdiobus_init()
199 	bus->write = mscc_miim_write;  in ocelot_mdiobus_init()
218 		if (priv->bus[i])  in ocelot_stop()
219 			mscc_miim_reset(priv->bus[i]);  in ocelot_stop()
227 	writel(0, priv->regs[QSYS] + QSYS_QMAP);  in ocelot_cpu_capture_setup()
231 		 * Do byte-swap and expect status after last data word  in ocelot_cpu_capture_setup()
235 		       priv->regs[QS] + QS_XTR_GRP_CFG(i));  in ocelot_cpu_capture_setup()
240 		       priv->regs[QS] + QS_INJ_GRP_CFG(i));  in ocelot_cpu_capture_setup()
247 		       priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));  in ocelot_cpu_capture_setup()
253 	       MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));  in ocelot_cpu_capture_setup()
257 	       priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));  in ocelot_cpu_capture_setup()
260 	setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),  in ocelot_cpu_capture_setup()
263 	/* No pause on CPU port - not needed (off by default) */  in ocelot_cpu_capture_setup()
264 	clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),  in ocelot_cpu_capture_setup()
267 	setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));  in ocelot_cpu_capture_setup()
272 	void __iomem *regs = priv->regs[port];  in ocelot_port_init()
302 	       MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));  in ocelot_port_init()
305 	setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0),  in ocelot_port_init()
313 	       priv->regs[SYS] + SYS_SYSTEM_RST_CFG);  in ocelot_switch_init()
316 	if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,  in ocelot_switch_init()
319 		return -EIO;  in ocelot_switch_init()
323 	setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,  in ocelot_switch_init()
338 	 * Disable port-to-port by switching  in ocelot_initialize()
339 	 * Put fron ports in "port isolation modes" - i.e. they cant send  in ocelot_initialize()
340 	 * to other ports - via the PGID sorce masks.  in ocelot_initialize()
343 		writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));  in ocelot_initialize()
346 	mscc_flush(priv->regs[QS], ocelot_regs_qs);  in ocelot_initialize()
348 	/* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */  in ocelot_initialize()
350 	       priv->regs[SYS] + SYS_FRM_AGING);  in ocelot_initialize()
367 	mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,  in ocelot_write_hwaddr()
368 			   pdata->enetaddr, PGID_UNICAST);  in ocelot_write_hwaddr()
370 	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));  in ocelot_write_hwaddr()
388 	mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,  in ocelot_start()
392 	       priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));  in ocelot_start()
395 	mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,  in ocelot_start()
396 			   pdata->enetaddr, PGID_UNICAST);  in ocelot_start()
398 	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));  in ocelot_start()
413 	 * The IFH is a 128bit-value  in ocelot_send()
415 	 * bit 56-67: destination mask  in ocelot_send()
416 	 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame  in ocelot_send()
417 	 * bit 20-27: cpu extraction queue mask  in ocelot_send()
418 	 * bit 16: tag type 0: C-tag, 1: S-tag  in ocelot_send()
419 	 * bit 0-11: VID  in ocelot_send()
426 	return mscc_send(priv->regs[QS], ocelot_regs_qs,  in ocelot_send()
436 	byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,  in ocelot_recv()
466 		priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);  in ocelot_probe()
467 		if (!priv->regs[reg[i].id]) {  in ocelot_probe()
471 			return -ENOMEM;  in ocelot_probe()
475 	priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);  in ocelot_probe()
478 		phy_connect(priv->bus[INTERNAL], i, dev,  in ocelot_probe()
491 		mdio_unregister(priv->bus[i]);  in ocelot_remove()
492 		mdio_free(priv->bus[i]);  in ocelot_remove()
507 	{.compatible = "mscc,vsc7514-switch"},
511 U_BOOT_DRIVER(ocelot) = {
512 	.name     = "ocelot-switch",