Lines Matching defs:x

22 #define ANA_PORT_VLAN_CFG(x)		(0x00 + 0x80 * (x))  argument
24 #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18) argument
25 #define ANA_PORT_CPU_FWD_CFG(x) (0x50 + 0x80 * (x)) argument
27 #define ANA_PORT_PORT_CFG(x) (0x60 + 0x80 * (x)) argument
29 #define ANA_PGID(x) (0x1000 + 4 * (x)) argument
37 #define SYS_PORT_MODE(x) (0x81bc + 0x4 * (x)) argument
39 #define SYS_SWITCH_PORT_MODE(x) (0x8294 + 0x4 * (x)) argument
44 #define REW_PORT_CFG(x) (0x8 + 0x80 * (x)) argument
52 #define QS_XTR_MAP(x) (0x10 + 4 * (x)) argument
59 #define HSIO_RCOMP_CFG_CFG0_MODE_SEL(x) ((x) << 8) argument
65 #define HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(x) ((x) << 1) argument
66 #define HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(x) ((x) << 5) argument
67 #define HSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(x) ((x) << 10) argument
68 #define HSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(x) ((x) << 13) argument
70 #define HSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(x) (x) argument
71 #define HSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(x) ((x) << 4) argument
72 #define HSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(x) ((x) << 7) argument
73 #define HSIO_SERDES6G_ANA_CFG_IB_CFG_RT(x) ((x) << 9) argument
74 #define HSIO_SERDES6G_ANA_CFG_IB_CFG_RF(x) ((x) << 14) argument
81 #define HSIO_SERDES6G_ANA_CFG_IB_CFG1_C(x) ((x) << 8) argument
83 #define HSIO_SERDES6G_ANA_CFG_OB_CFG_SR(x) ((x) << 4) argument
85 #define HSIO_SERDES6G_ANA_CFG_OB_CFG_POST0(x) ((x) << 23) argument
89 #define HSIO_SERDES6G_ANA_CFG_OB_CFG1_LEV(x) (x) argument
90 #define HSIO_SERDES6G_ANA_CFG_OB_CFG1_ENA_CAS(x) ((x) << 6) argument
92 #define HSIO_SERDES6G_ANA_CFG_COMMON_CFG_IF_MODE(x) (x) argument
97 #define HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8) argument
103 #define HSIO_MCB_SERDES6G_CFG_ADDR(x) (x) argument
118 #define DEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8) argument
119 #define DEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4) argument
120 #define DEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x) argument
126 #define DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16) argument