1 // SPDX-License-Identifier: GPL-2.0+
5  *	Roy Zang <tie-fei.zang@freescale.com>
43 	struct memac_mdio_controller *regs = bus->priv;  in memac_mdio_write()
49 		memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);  in memac_mdio_write()
51 		memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);  in memac_mdio_write()
53 	/* Wait till the bus is free */  in memac_mdio_write()
54 	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)  in memac_mdio_write()
59 	memac_out_32(&regs->mdio_ctl, mdio_ctl);  in memac_mdio_write()
63 		memac_out_32(&regs->mdio_addr, regnum & 0xffff);  in memac_mdio_write()
65 	/* Wait till the bus is free */  in memac_mdio_write()
66 	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)  in memac_mdio_write()
70 	memac_out_32(&regs->mdio_data, MDIO_DATA(value));  in memac_mdio_write()
72 	/* Wait till the MDIO write is complete */  in memac_mdio_write()
73 	while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)  in memac_mdio_write()
88 	struct memac_mdio_controller *regs = bus->priv;  in memac_mdio_read()
92 		if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))  in memac_mdio_read()
96 		memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);  in memac_mdio_read()
98 		memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);  in memac_mdio_read()
100 	/* Wait till the bus is free */  in memac_mdio_read()
101 	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)  in memac_mdio_read()
106 	memac_out_32(&regs->mdio_ctl, mdio_ctl);  in memac_mdio_read()
110 		memac_out_32(&regs->mdio_addr, regnum & 0xffff);  in memac_mdio_read()
112 	/* Wait till the bus is free */  in memac_mdio_read()
113 	while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)  in memac_mdio_read()
116 	/* Initiate the read */  in memac_mdio_read()
118 	memac_out_32(&regs->mdio_ctl, mdio_ctl);  in memac_mdio_read()
120 	/* Wait till the MDIO write is complete */  in memac_mdio_read()
121 	while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)  in memac_mdio_read()
125 	if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)  in memac_mdio_read()
128 	return memac_in_32(&regs->mdio_data) & 0xffff;  in memac_mdio_read()
142 		return -1;  in fm_memac_mdio_init()
145 	bus->read = memac_mdio_read;  in fm_memac_mdio_init()
146 	bus->write = memac_mdio_write;  in fm_memac_mdio_init()
147 	bus->reset = memac_mdio_reset;  in fm_memac_mdio_init()
148 	strcpy(bus->name, info->name);  in fm_memac_mdio_init()
150 	bus->priv = info->regs;  in fm_memac_mdio_init()
153 	 * On some platforms like B4860, default value of MDIO_CLK_DIV bits  in fm_memac_mdio_init()
156 	 * On other platforms like T1040, default value of MDIO_CLK_DIV bits  in fm_memac_mdio_init()
160 	 * NEG bit default should be '1' as per FMAN-v3 RM, but on platform  in fm_memac_mdio_init()
162 	 * on XAUI PHY, so set this bit definitely.  in fm_memac_mdio_init()
165 		&((struct memac_mdio_controller *)info->regs)->mdio_stat,  in fm_memac_mdio_init()