Lines Matching +full:save +full:- +full:mac +full:- +full:address
1 // SPDX-License-Identifier: GPL-2.0+
3 * Cirrus Logic EP93xx ethernet MAC / MII driver.
9 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
28 #define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
29 #define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
47 printf(" rx_dq.base %p\n", priv->rx_dq.base); in dump_dev()
48 printf(" rx_dq.current %p\n", priv->rx_dq.current); in dump_dev()
49 printf(" rx_dq.end %p\n", priv->rx_dq.end); in dump_dev()
50 printf(" rx_sq.base %p\n", priv->rx_sq.base); in dump_dev()
51 printf(" rx_sq.current %p\n", priv->rx_sq.current); in dump_dev()
52 printf(" rx_sq.end %p\n", priv->rx_sq.end); in dump_dev()
57 printf(" tx_dq.base %p\n", priv->tx_dq.base); in dump_dev()
58 printf(" tx_dq.current %p\n", priv->tx_dq.current); in dump_dev()
59 printf(" tx_dq.end %p\n", priv->tx_dq.end); in dump_dev()
60 printf(" tx_sq.base %p\n", priv->tx_sq.base); in dump_dev()
61 printf(" tx_sq.current %p\n", priv->tx_sq.current); in dump_dev()
62 printf(" tx_sq.end %p\n", priv->tx_sq.end); in dump_dev()
74 printf(" descriptor address word1 word2\n"); in dump_rx_status_queue()
77 priv->rx_sq.base + i, in dump_rx_status_queue()
78 (priv->rx_sq.base + i)->word1, in dump_rx_status_queue()
79 (priv->rx_sq.base + i)->word2); in dump_rx_status_queue()
92 printf(" descriptor address word1 word2\n"); in dump_rx_descriptor_queue()
95 priv->rx_dq.base + i, in dump_rx_descriptor_queue()
96 (priv->rx_dq.base + i)->word1, in dump_rx_descriptor_queue()
97 (priv->rx_dq.base + i)->word2); in dump_rx_descriptor_queue()
110 printf(" descriptor address word1 word2\n"); in dump_tx_descriptor_queue()
113 priv->tx_dq.base + i, in dump_tx_descriptor_queue()
114 (priv->tx_dq.base + i)->word1, in dump_tx_descriptor_queue()
115 (priv->tx_dq.base + i)->word2); in dump_tx_descriptor_queue()
128 printf(" descriptor address word1\n"); in dump_tx_status_queue()
131 priv->rx_sq.base + i, in dump_tx_status_queue()
132 (priv->rx_sq.base + i)->word1); in dump_tx_status_queue()
144 * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
149 struct mac_regs *mac = GET_REGS(dev); in ep93xx_mac_reset() local
154 value = readl(&mac->selfctl); in ep93xx_mac_reset()
156 writel(value, &mac->selfctl); in ep93xx_mac_reset()
158 while (readl(&mac->selfctl) & SELFCTL_RESET) in ep93xx_mac_reset()
161 debug("-ep93xx_mac_reset"); in ep93xx_mac_reset()
168 struct mac_regs *mac = GET_REGS(dev); in ep93xx_eth_open() local
169 uchar *mac_addr = dev->enetaddr; in ep93xx_eth_open()
174 /* Reset the MAC */ in ep93xx_eth_open()
177 /* Reset the descriptor queues' current and end address values */ in ep93xx_eth_open()
178 priv->tx_dq.current = priv->tx_dq.base; in ep93xx_eth_open()
179 priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC); in ep93xx_eth_open()
181 priv->tx_sq.current = priv->tx_sq.base; in ep93xx_eth_open()
182 priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC); in ep93xx_eth_open()
184 priv->rx_dq.current = priv->rx_dq.base; in ep93xx_eth_open()
185 priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC); in ep93xx_eth_open()
187 priv->rx_sq.current = priv->rx_sq.base; in ep93xx_eth_open()
188 priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC); in ep93xx_eth_open()
191 * Set the transmit descriptor and status queues' base address, in ep93xx_eth_open()
192 * current address, and length registers. Set the maximum frame in ep93xx_eth_open()
195 writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd); in ep93xx_eth_open()
196 writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd); in ep93xx_eth_open()
197 writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen); in ep93xx_eth_open()
199 writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd); in ep93xx_eth_open()
200 writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd); in ep93xx_eth_open()
201 writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen); in ep93xx_eth_open()
203 writel(0x00040000, &mac->txdthrshld); in ep93xx_eth_open()
204 writel(0x00040000, &mac->txststhrshld); in ep93xx_eth_open()
206 writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen); in ep93xx_eth_open()
207 writel(BMCTL_TXEN, &mac->bmctl); in ep93xx_eth_open()
210 * Set the receive descriptor and status queues' base address, in ep93xx_eth_open()
211 * current address, and length registers. Enable the receive in ep93xx_eth_open()
214 writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd); in ep93xx_eth_open()
215 writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd); in ep93xx_eth_open()
216 writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen); in ep93xx_eth_open()
218 writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd); in ep93xx_eth_open()
219 writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd); in ep93xx_eth_open()
220 writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen); in ep93xx_eth_open()
222 writel(0x00040000, &mac->rxdthrshld); in ep93xx_eth_open()
224 writel(BMCTL_RXEN, &mac->bmctl); in ep93xx_eth_open()
226 writel(0x00040000, &mac->rxststhrshld); in ep93xx_eth_open()
229 while (!(readl(&mac->bmsts) & BMSTS_RXACT)) in ep93xx_eth_open()
235 * status entries to the MAC. in ep93xx_eth_open()
238 /* set buffer address */ in ep93xx_eth_open()
239 (priv->rx_dq.base + i)->word1 = (uint32_t)net_rx_packets[i]; in ep93xx_eth_open()
242 (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN; in ep93xx_eth_open()
245 memset(priv->tx_dq.base, 0, in ep93xx_eth_open()
247 memset(priv->rx_sq.base, 0, in ep93xx_eth_open()
249 memset(priv->tx_sq.base, 0, in ep93xx_eth_open()
252 writel(NUMRXDESC, &mac->rxdqenq); in ep93xx_eth_open()
253 writel(NUMRXDESC, &mac->rxstsqenq); in ep93xx_eth_open()
255 /* Set the primary MAC address */ in ep93xx_eth_open()
256 writel(AFP_IAPRIMARY, &mac->afp); in ep93xx_eth_open()
259 &mac->indad); in ep93xx_eth_open()
260 writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper); in ep93xx_eth_open()
264 RXCTL_RCRCA | RXCTL_MA, &mac->rxctl); in ep93xx_eth_open()
265 writel(TXCTL_STXON, &mac->txctl); in ep93xx_eth_open()
274 debug("-ep93xx_eth_open"); in ep93xx_eth_open()
280 * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
285 struct mac_regs *mac = GET_REGS(dev); in ep93xx_eth_close() local
289 writel(0x00000000, &mac->rxctl); in ep93xx_eth_close()
290 writel(0x00000000, &mac->txctl); in ep93xx_eth_close()
292 debug("-ep93xx_eth_close"); in ep93xx_eth_close()
296 * Copy a frame of data from the MAC into the protocol layer for further
301 struct mac_regs *mac = GET_REGS(dev); in ep93xx_eth_rcv_packet() local
303 int len = -1; in ep93xx_eth_rcv_packet()
307 if (RX_STATUS_RFP(priv->rx_sq.current)) { in ep93xx_eth_rcv_packet()
308 if (RX_STATUS_RWE(priv->rx_sq.current)) { in ep93xx_eth_rcv_packet()
318 len = RX_STATUS_FRAME_LEN(priv->rx_sq.current); in ep93xx_eth_rcv_packet()
321 (uchar *)priv->rx_dq.current->word1, len); in ep93xx_eth_rcv_packet()
327 priv->rx_sq.current->word1, in ep93xx_eth_rcv_packet()
328 priv->rx_sq.current->word2); in ep93xx_eth_rcv_packet()
339 memset((void *)priv->rx_sq.current, 0, in ep93xx_eth_rcv_packet()
342 priv->rx_sq.current++; in ep93xx_eth_rcv_packet()
343 if (priv->rx_sq.current >= priv->rx_sq.end) in ep93xx_eth_rcv_packet()
344 priv->rx_sq.current = priv->rx_sq.base; in ep93xx_eth_rcv_packet()
346 priv->rx_dq.current++; in ep93xx_eth_rcv_packet()
347 if (priv->rx_dq.current >= priv->rx_dq.end) in ep93xx_eth_rcv_packet()
348 priv->rx_dq.current = priv->rx_dq.base; in ep93xx_eth_rcv_packet()
352 * back to the MAC engine, and loop again, checking for in ep93xx_eth_rcv_packet()
355 writel(1, &mac->rxdqenq); in ep93xx_eth_rcv_packet()
356 writel(1, &mac->rxstsqenq); in ep93xx_eth_rcv_packet()
361 debug("-ep93xx_eth_rcv_packet %d", len); in ep93xx_eth_rcv_packet()
371 struct mac_regs *mac = GET_REGS(dev); in ep93xx_eth_send_packet() local
373 int ret = -1; in ep93xx_eth_send_packet()
383 * to the MAC for transmission. in ep93xx_eth_send_packet()
386 /* set buffer address */ in ep93xx_eth_send_packet()
387 priv->tx_dq.current->word1 = (uint32_t)packet; in ep93xx_eth_send_packet()
390 priv->tx_dq.current->word2 = length | TX_DESC_EOF; in ep93xx_eth_send_packet()
393 priv->tx_sq.current->word1 = 0; in ep93xx_eth_send_packet()
396 writel(1, &mac->txdqenq); in ep93xx_eth_send_packet()
399 while (!TX_STATUS_TXFP(priv->tx_sq.current)) in ep93xx_eth_send_packet()
402 if (!TX_STATUS_TXWE(priv->tx_sq.current)) { in ep93xx_eth_send_packet()
404 priv->tx_sq.current->word1); in ep93xx_eth_send_packet()
416 debug("-ep93xx_eth_send_packet %d", ret); in ep93xx_eth_send_packet()
426 return -ENOMEM; in ep93xx_miiphy_initialize()
427 strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN); in ep93xx_miiphy_initialize()
428 mdiodev->read = ep93xx_miiphy_read; in ep93xx_miiphy_initialize()
429 mdiodev->write = ep93xx_miiphy_write; in ep93xx_miiphy_initialize()
439 * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
441 * as well as for received packets. The EP93XX MAC hardware is initialized.
446 int ret = -1; in ep93xx_eth_initialize()
459 priv->regs = (struct mac_regs *)base_addr; in ep93xx_eth_initialize()
461 priv->tx_dq.base = calloc(NUMTXDESC, in ep93xx_eth_initialize()
463 if (priv->tx_dq.base == NULL) { in ep93xx_eth_initialize()
468 priv->tx_sq.base = calloc(NUMTXDESC, in ep93xx_eth_initialize()
470 if (priv->tx_sq.base == NULL) { in ep93xx_eth_initialize()
475 priv->rx_dq.base = calloc(NUMRXDESC, in ep93xx_eth_initialize()
477 if (priv->rx_dq.base == NULL) { in ep93xx_eth_initialize()
482 priv->rx_sq.base = calloc(NUMRXDESC, in ep93xx_eth_initialize()
484 if (priv->rx_sq.base == NULL) { in ep93xx_eth_initialize()
496 dev->iobase = base_addr; in ep93xx_eth_initialize()
497 dev->priv = priv; in ep93xx_eth_initialize()
498 dev->init = ep93xx_eth_open; in ep93xx_eth_initialize()
499 dev->halt = ep93xx_eth_close; in ep93xx_eth_initialize()
500 dev->send = ep93xx_eth_send_packet; in ep93xx_eth_initialize()
501 dev->recv = ep93xx_eth_rcv_packet; in ep93xx_eth_initialize()
503 sprintf(dev->name, "ep93xx_eth-%hu", dev_num); in ep93xx_eth_initialize()
512 free(priv->rx_sq.base); in ep93xx_eth_initialize()
516 free(priv->rx_dq.base); in ep93xx_eth_initialize()
520 free(priv->tx_sq.base); in ep93xx_eth_initialize()
524 free(priv->tx_dq.base); in ep93xx_eth_initialize()
535 debug("-ep93xx_eth_initialize %d", ret); in ep93xx_eth_initialize()
542 * Maximum MII address we support
547 * Maximum MII register address we support
552 * Read a 16-bit value from an MII register.
558 struct mac_regs *mac = (struct mac_regs *)MAC_BASE; in ep93xx_miiphy_read() local
559 int ret = -1; in ep93xx_miiphy_read()
565 BUG_ON(bus->name == NULL); in ep93xx_miiphy_read()
570 * Save the current SelfCTL register value. Set MAC to suppress in ep93xx_miiphy_read()
574 self_ctl = readl(&mac->selfctl); in ep93xx_miiphy_read()
576 writel(self_ctl & ~(1 << 8), &mac->selfctl); in ep93xx_miiphy_read()
579 while (readl(&mac->miists) & MIISTS_BUSY) in ep93xx_miiphy_read()
587 &mac->miicmd); in ep93xx_miiphy_read()
588 while (readl(&mac->miists) & MIISTS_BUSY) in ep93xx_miiphy_read()
591 value = (unsigned short)readl(&mac->miidata); in ep93xx_miiphy_read()
594 writel(self_ctl, &mac->selfctl); in ep93xx_miiphy_read()
599 debug("-ep93xx_miiphy_read"); in ep93xx_miiphy_read()
606 * Write a 16-bit value to an MII register.
611 struct mac_regs *mac = (struct mac_regs *)MAC_BASE; in ep93xx_miiphy_write() local
612 int ret = -1; in ep93xx_miiphy_write()
618 BUG_ON(bus->name == NULL); in ep93xx_miiphy_write()
623 * Save the current SelfCTL register value. Set MAC to suppress in ep93xx_miiphy_write()
627 self_ctl = readl(&mac->selfctl); in ep93xx_miiphy_write()
629 writel(self_ctl & ~(1 << 8), &mac->selfctl); in ep93xx_miiphy_write()
632 while (readl(&mac->miists) & MIISTS_BUSY) in ep93xx_miiphy_write()
636 writel((uint32_t)value, &mac->miidata); in ep93xx_miiphy_write()
638 &mac->miicmd); in ep93xx_miiphy_write()
639 while (readl(&mac->miists) & MIISTS_BUSY) in ep93xx_miiphy_write()
643 writel(self_ctl, &mac->selfctl); in ep93xx_miiphy_write()
648 debug("-ep93xx_miiphy_write"); in ep93xx_miiphy_write()