106 static u8 DM9000_ior(int);
131 	DM9000_DBG("NCR   (0x00): %02x\n", DM9000_ior(0));  in dump_regs()
132 	DM9000_DBG("NSR   (0x01): %02x\n", DM9000_ior(1));  in dump_regs()
133 	DM9000_DBG("TCR   (0x02): %02x\n", DM9000_ior(2));  in dump_regs()
134 	DM9000_DBG("TSRI  (0x03): %02x\n", DM9000_ior(3));  in dump_regs()
135 	DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));  in dump_regs()
136 	DM9000_DBG("RCR   (0x05): %02x\n", DM9000_ior(5));  in dump_regs()
137 	DM9000_DBG("RSR   (0x06): %02x\n", DM9000_ior(6));  in dump_regs()
138 	DM9000_DBG("ISR   (0xFE): %02x\n", DM9000_ior(DM9000_ISR));  in dump_regs()
229 	id_val = DM9000_ior(DM9000_VIDL);  in dm9000_probe()
230 	id_val |= DM9000_ior(DM9000_VIDH) << 8;  in dm9000_probe()
231 	id_val |= DM9000_ior(DM9000_PIDL) << 16;  in dm9000_probe()
232 	id_val |= DM9000_ior(DM9000_PIDH) << 24;  in dm9000_probe()
263 	} while (DM9000_ior(DM9000_NCR) & 1);  in dm9000_reset()
271 	} while (DM9000_ior(DM9000_NCR) & 1);  in dm9000_reset()
274 	if ((DM9000_ior(DM9000_PIDL) != 0x0) ||  in dm9000_reset()
275 	    (DM9000_ior(DM9000_PIDH) != 0x90))  in dm9000_reset()
296 	io_mode = DM9000_ior(DM9000_ISR) >> 6;  in dm9000_init()
356 		DM9000_DBG("%02x:", DM9000_ior(oft));  in dm9000_init()
427 	while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||  in dm9000_send()
428 		!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {  in dm9000_send()
467 	if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */  in dm9000_rx()
474 		DM9000_ior(DM9000_MRCMDX);	/* Dummy read */  in dm9000_rx()
538 	to[0] = DM9000_ior(DM9000_EPDRL);  in dm9000_read_srom_word()
539 	to[1] = DM9000_ior(DM9000_EPDRH);  in dm9000_read_srom_word()
566 DM9000_ior(int reg)  in DM9000_ior()  function
595 	val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);  in dm9000_phy_read()