Lines Matching refs:u32
122 u32 lo;
123 u32 hi;
135 u32 cmd_sts; /* Command/status field */
143 u32 cmd_sts; /* Descriptor command status */
155 u32 phyadr; /* PHY Address */
156 u32 pad1[3];
157 u32 smi; /* SMI */
158 u32 pad2[0xFB];
159 u32 pconf; /* Port configuration */
160 u32 pad3;
161 u32 pconf_ext; /* Port configuration extend */
162 u32 pad4;
163 u32 pcmd; /* Port Command */
164 u32 pad5;
165 u32 pstatus; /* Port Status */
166 u32 pad6;
167 u32 spar; /* Serial Parameters */
168 u32 pad7;
169 u32 htpr; /* Hash table pointer */
170 u32 pad8;
171 u32 fcsal; /* Flow control source address low */
172 u32 pad9;
173 u32 fcsah; /* Flow control source address high */
174 u32 pad10;
175 u32 sdma_conf; /* SDMA configuration */
176 u32 pad11;
177 u32 sdma_cmd; /* SDMA command */
178 u32 pad12;
179 u32 ic; /* Interrupt cause */
180 u32 iwc; /* Interrupt write to clear */
181 u32 im; /* Interrupt mask */
182 u32 pad13;
183 u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
185 u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
186 u32 pad14[3];
189 u32 pad15[4];
192 u32 pad16[0x0C];