Lines Matching +full:spi +full:- +full:nor
1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/mtd/spi-nor.h>
21 #include <spi-mem.h>
22 #include <spi.h>
29 * For everything but full-chip erase; probably could be much smaller, but kept
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op in spi_nor_read_write_reg() argument
40 if (op->data.dir == SPI_MEM_DATA_IN) in spi_nor_read_write_reg()
41 op->data.buf.in = buf; in spi_nor_read_write_reg()
43 op->data.buf.out = buf; in spi_nor_read_write_reg()
44 return spi_mem_exec_op(nor->spi, op); in spi_nor_read_write_reg()
47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) in spi_nor_read_reg() argument
55 ret = spi_nor_read_write_reg(nor, &op, val); in spi_nor_read_reg()
57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret, in spi_nor_read_reg()
63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) in spi_nor_write_reg() argument
70 return spi_nor_read_write_reg(nor, &op, buf); in spi_nor_write_reg()
73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, in spi_nor_read_data() argument
77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), in spi_nor_read_data()
78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), in spi_nor_read_data()
79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1), in spi_nor_read_data()
85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); in spi_nor_read_data()
86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); in spi_nor_read_data()
88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); in spi_nor_read_data()
91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; in spi_nor_read_data()
95 ret = spi_mem_adjust_op_size(nor->spi, &op); in spi_nor_read_data()
99 ret = spi_mem_exec_op(nor->spi, &op); in spi_nor_read_data()
104 remaining -= op.data.nbytes; in spi_nor_read_data()
117 static int read_cr(struct spi_nor *nor) in read_cr() argument
122 ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1); in read_cr()
124 dev_dbg(nor->dev, "error %d reading CR\n", ret); in read_cr()
136 static inline int write_sr(struct spi_nor *nor, u8 val) in write_sr() argument
138 nor->cmd_buf[0] = val; in write_sr()
139 return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); in write_sr()
146 static inline int write_enable(struct spi_nor *nor) in write_enable() argument
148 return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0); in write_enable()
154 static inline int write_disable(struct spi_nor *nor) in write_disable() argument
156 return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0); in write_disable()
161 return mtd->priv; in mtd_to_spi_nor()
191 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, in spi_nor_set_4byte_opcodes() argument
194 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); in spi_nor_set_4byte_opcodes()
197 /* Enable/disable 4-byte addressing mode. */
198 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, in set_4byte() argument
213 write_enable(nor); in set_4byte()
216 status = spi_nor_write_reg(nor, cmd, NULL, 0); in set_4byte()
218 write_disable(nor); in set_4byte()
225 * 3-byte-address reads come from the second 16M. in set_4byte()
228 write_enable(nor); in set_4byte()
229 nor->cmd_buf[0] = 0; in set_4byte()
230 spi_nor_write_reg(nor, SPINOR_OP_WREAR, in set_4byte()
231 nor->cmd_buf, 1); in set_4byte()
232 write_disable(nor); in set_4byte()
238 nor->cmd_buf[0] = enable << 7; in set_4byte()
239 return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); in set_4byte()
251 static int read_sr(struct spi_nor *nor) in read_sr() argument
256 ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1); in read_sr()
270 static int read_fsr(struct spi_nor *nor) in read_fsr() argument
275 ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1); in read_fsr()
284 static int spi_nor_sr_ready(struct spi_nor *nor) in spi_nor_sr_ready() argument
286 int sr = read_sr(nor); in spi_nor_sr_ready()
294 static int spi_nor_fsr_ready(struct spi_nor *nor) in spi_nor_fsr_ready() argument
296 int fsr = read_fsr(nor); in spi_nor_fsr_ready()
303 static int spi_nor_ready(struct spi_nor *nor) in spi_nor_ready() argument
307 sr = spi_nor_sr_ready(nor); in spi_nor_ready()
310 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; in spi_nor_ready()
318 * Returns non-zero if error.
320 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, in spi_nor_wait_till_ready_with_timeout() argument
329 ret = spi_nor_ready(nor); in spi_nor_wait_till_ready_with_timeout()
336 dev_err(nor->dev, "flash operation timed out\n"); in spi_nor_wait_till_ready_with_timeout()
338 return -ETIMEDOUT; in spi_nor_wait_till_ready_with_timeout()
341 static int spi_nor_wait_till_ready(struct spi_nor *nor) in spi_nor_wait_till_ready() argument
343 return spi_nor_wait_till_ready_with_timeout(nor, in spi_nor_wait_till_ready()
349 * Erase an address range on the nor chip. The address range may extend
354 return -ENOTSUPP; in spi_nor_erase()
357 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) in spi_nor_read_id() argument
363 tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); in spi_nor_read_id()
365 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); in spi_nor_read_id()
370 for (; info->sector_size != 0; info++) { in spi_nor_read_id()
371 if (info->id_len) { in spi_nor_read_id()
372 if (!memcmp(info->id, id, info->id_len)) in spi_nor_read_id()
376 dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", in spi_nor_read_id()
378 return ERR_PTR(-ENODEV); in spi_nor_read_id()
384 struct spi_nor *nor = mtd_to_spi_nor(mtd); in spi_nor_read() local
387 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); in spi_nor_read()
392 ret = spi_nor_read_data(nor, addr, len, buf); in spi_nor_read()
394 /* We shouldn't see 0-length reads */ in spi_nor_read()
395 ret = -EIO; in spi_nor_read()
404 len -= ret; in spi_nor_read()
413 * Write an address range to the nor chip. Data must be written in
420 return -ENOTSUPP; in spi_nor_write()
425 * macronix_quad_enable() - set QE bit in Status Register.
426 * @nor: pointer to a 'struct spi_nor'
432 * Return: 0 on success, -errno otherwise.
434 static int macronix_quad_enable(struct spi_nor *nor) in macronix_quad_enable() argument
438 val = read_sr(nor); in macronix_quad_enable()
444 write_enable(nor); in macronix_quad_enable()
446 write_sr(nor, val | SR_QUAD_EN_MX); in macronix_quad_enable()
448 ret = spi_nor_wait_till_ready(nor); in macronix_quad_enable()
452 ret = read_sr(nor); in macronix_quad_enable()
454 dev_err(nor->dev, "Macronix Quad bit not set\n"); in macronix_quad_enable()
455 return -EINVAL; in macronix_quad_enable()
469 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) in write_sr_cr() argument
473 write_enable(nor); in write_sr_cr()
475 ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); in write_sr_cr()
477 dev_dbg(nor->dev, in write_sr_cr()
479 return -EINVAL; in write_sr_cr()
482 ret = spi_nor_wait_till_ready(nor); in write_sr_cr()
484 dev_dbg(nor->dev, in write_sr_cr()
493 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
494 * @nor: pointer to a 'struct spi_nor'
503 * Return: 0 on success, -errno otherwise.
505 static int spansion_read_cr_quad_enable(struct spi_nor *nor) in spansion_read_cr_quad_enable() argument
511 ret = read_cr(nor); in spansion_read_cr_quad_enable()
514 return -EINVAL; in spansion_read_cr_quad_enable()
523 ret = read_sr(nor); in spansion_read_cr_quad_enable()
526 return -EINVAL; in spansion_read_cr_quad_enable()
530 ret = write_sr_cr(nor, sr_cr); in spansion_read_cr_quad_enable()
535 ret = read_cr(nor); in spansion_read_cr_quad_enable()
537 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); in spansion_read_cr_quad_enable()
538 return -EINVAL; in spansion_read_cr_quad_enable()
556 /* Quad SPI */
574 read->num_mode_clocks = num_mode_clocks; in spi_nor_set_read_settings()
575 read->num_wait_states = num_wait_states; in spi_nor_set_read_settings()
576 read->opcode = opcode; in spi_nor_set_read_settings()
577 read->proto = proto; in spi_nor_set_read_settings()
580 static int spi_nor_init_params(struct spi_nor *nor, in spi_nor_init_params() argument
585 params->hwcaps.mask = SNOR_HWCAPS_READ; in spi_nor_init_params()
586 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], in spi_nor_init_params()
590 if (!(info->flags & SPI_NOR_NO_FR)) { in spi_nor_init_params()
591 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; in spi_nor_init_params()
592 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], in spi_nor_init_params()
597 if (info->flags & SPI_NOR_QUAD_READ) { in spi_nor_init_params()
598 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; in spi_nor_init_params()
599 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], in spi_nor_init_params()
607 static int spi_nor_select_read(struct spi_nor *nor, in spi_nor_select_read() argument
616 return -EINVAL; in spi_nor_select_read()
625 read = ¶ms->reads[cmd]; in spi_nor_select_read()
626 nor->read_opcode = read->opcode; in spi_nor_select_read()
627 nor->read_proto = read->proto; in spi_nor_select_read()
630 * In the spi-nor framework, we don't need to make the difference in spi_nor_select_read()
633 * flash memory to know whether it should enter or leave its 0-4-4 in spi_nor_select_read()
635 * eXecution In Place is out of the scope of the mtd sub-system. in spi_nor_select_read()
639 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; in spi_nor_select_read()
643 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, in spi_nor_setup() argument
651 * Keep only the hardware capabilities supported by both the SPI in spi_nor_setup()
652 * controller and the SPI flash memory. in spi_nor_setup()
654 shared_mask = hwcaps->mask & params->hwcaps.mask; in spi_nor_setup()
657 err = spi_nor_select_read(nor, params, shared_mask); in spi_nor_setup()
659 dev_dbg(nor->dev, in spi_nor_setup()
660 "can't select read settings supported by both the SPI controller and memory.\n"); in spi_nor_setup()
665 if (spi_nor_get_protocol_width(nor->read_proto) == 4) { in spi_nor_setup()
669 err = macronix_quad_enable(nor); in spi_nor_setup()
679 err = spansion_read_cr_quad_enable(nor); in spi_nor_setup()
685 dev_dbg(nor->dev, "quad mode not supported\n"); in spi_nor_setup()
692 static int spi_nor_init(struct spi_nor *nor) in spi_nor_init() argument
694 if (nor->addr_width == 4 && in spi_nor_init()
695 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && in spi_nor_init()
696 !(nor->info->flags & SPI_NOR_4B_OPCODES)) { in spi_nor_init()
704 if (nor->flags & SNOR_F_BROKEN_RESET) in spi_nor_init()
706 set_4byte(nor, nor->info, 1); in spi_nor_init()
712 int spi_nor_scan(struct spi_nor *nor) in spi_nor_scan() argument
716 struct mtd_info *mtd = &nor->mtd; in spi_nor_scan()
721 struct spi_slave *spi = nor->spi; in spi_nor_scan() local
724 /* Reset SPI protocol for all commands. */ in spi_nor_scan()
725 nor->reg_proto = SNOR_PROTO_1_1_1; in spi_nor_scan()
726 nor->read_proto = SNOR_PROTO_1_1_1; in spi_nor_scan()
727 nor->write_proto = SNOR_PROTO_1_1_1; in spi_nor_scan()
729 if (spi->mode & SPI_RX_QUAD) in spi_nor_scan()
732 info = spi_nor_read_id(nor); in spi_nor_scan()
734 return -ENOENT; in spi_nor_scan()
736 ret = spi_nor_init_params(nor, info, ¶ms); in spi_nor_scan()
740 mtd->name = "spi-flash"; in spi_nor_scan()
741 mtd->priv = nor; in spi_nor_scan()
742 mtd->type = MTD_NORFLASH; in spi_nor_scan()
743 mtd->writesize = 1; in spi_nor_scan()
744 mtd->flags = MTD_CAP_NORFLASH; in spi_nor_scan()
745 mtd->size = info->sector_size * info->n_sectors; in spi_nor_scan()
746 mtd->_erase = spi_nor_erase; in spi_nor_scan()
747 mtd->_read = spi_nor_read; in spi_nor_scan()
748 mtd->_write = spi_nor_write; in spi_nor_scan()
750 nor->size = mtd->size; in spi_nor_scan()
752 if (info->flags & USE_FSR) in spi_nor_scan()
753 nor->flags |= SNOR_F_USE_FSR; in spi_nor_scan()
754 if (info->flags & USE_CLSR) in spi_nor_scan()
755 nor->flags |= SNOR_F_USE_CLSR; in spi_nor_scan()
757 if (info->flags & SPI_NOR_NO_FR) in spi_nor_scan()
761 * Configure the SPI memory: in spi_nor_scan()
762 * - select op codes for (Fast) Read, Page Program and Sector Erase. in spi_nor_scan()
763 * - set the number of dummy cycles (mode cycles + wait states). in spi_nor_scan()
764 * - set the SPI protocols for register and memory accesses. in spi_nor_scan()
765 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). in spi_nor_scan()
767 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); in spi_nor_scan()
771 if (nor->addr_width) { in spi_nor_scan()
773 } else if (info->addr_width) { in spi_nor_scan()
774 nor->addr_width = info->addr_width; in spi_nor_scan()
775 } else if (mtd->size > 0x1000000) { in spi_nor_scan()
776 /* enable 4-byte addressing if the device exceeds 16MiB */ in spi_nor_scan()
777 nor->addr_width = 4; in spi_nor_scan()
779 info->flags & SPI_NOR_4B_OPCODES) in spi_nor_scan()
780 spi_nor_set_4byte_opcodes(nor, info); in spi_nor_scan()
782 nor->addr_width = 3; in spi_nor_scan()
785 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { in spi_nor_scan()
787 nor->addr_width); in spi_nor_scan()
788 return -EINVAL; in spi_nor_scan()
791 /* Send all the required SPI flash commands to initialize device */ in spi_nor_scan()
792 nor->info = info; in spi_nor_scan()
793 ret = spi_nor_init(nor); in spi_nor_scan()
800 /* U-Boot specific functions, need to extend MTD to support these */
801 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) in spi_flash_cmd_get_sw_write_prot() argument
803 return -ENOTSUPP; in spi_flash_cmd_get_sw_write_prot()