123 #define zynq_nand_smc_base	((struct zynq_nand_smc_regs __iomem *)\  macro
249 	status = readl(&zynq_nand_smc_base->esr);  in zynq_nand_waitfor_ecc_completion()
251 		status = readl(&zynq_nand_smc_base->esr);  in zynq_nand_waitfor_ecc_completion()
274 	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);  in zynq_nand_init_nand_flash()
277 	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);  in zynq_nand_init_nand_flash()
280 		writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);  in zynq_nand_init_nand_flash()
282 		writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);  in zynq_nand_init_nand_flash()
284 	writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);  in zynq_nand_init_nand_flash()
294 	writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);  in zynq_nand_init_nand_flash()
295 	writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);  in zynq_nand_init_nand_flash()
327 		ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);  in zynq_nand_calculate_hwecc()
824 	writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);  in zynq_nand_cmd_function()
1021 	csr_val = readl(&zynq_nand_smc_base->csr);  in zynq_nand_device_ready()
1025 		writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);  in zynq_nand_device_ready()
1151 		ecc_cfg = readl(&zynq_nand_smc_base->emcr);  in zynq_nand_init()
1153 		writel(ecc_cfg, &zynq_nand_smc_base->emcr);  in zynq_nand_init()
1201 			       &zynq_nand_smc_base->emcr);  in zynq_nand_init()
1207 			       &zynq_nand_smc_base->emcr);  in zynq_nand_init()
1213 			       &zynq_nand_smc_base->emcr);  in zynq_nand_init()