Lines Matching refs:reg_val
117 u32 reg_val; in nand_waitfor_cmd_completion() local
128 reg_val = readl(®->dma_mst_ctrl); in nand_waitfor_cmd_completion()
136 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | in nand_waitfor_cmd_completion()
138 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) in nand_waitfor_cmd_completion()
207 int reg_val; in nand_dev_ready() local
212 reg_val = readl(&info->reg->status); in nand_dev_ready()
213 if (reg_val & STATUS_RBSY0) in nand_dev_ready()
239 u32 reg_val; in nand_clear_interrupt_status() local
242 reg_val = readl(®->isr); in nand_clear_interrupt_status()
243 writel(reg_val, ®->isr); in nand_clear_interrupt_status()
391 u32 reg_val; in check_ecc_error() local
400 reg_val = readl(®->dec_status); in check_ecc_error()
401 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) { in check_ecc_error()
402 reg_val = readl(®->bch_dec_status_buf); in check_ecc_error()
408 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) && in check_ecc_error()
413 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) { in check_ecc_error()
414 reg_val = readl(®->bch_dec_status_buf); in check_ecc_error()
420 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) && in check_ecc_error()
435 u32 reg_val; in start_command() local
437 reg_val = readl(®->command); in start_command()
438 reg_val |= CMD_GO; in start_command()
439 writel(reg_val, ®->command); in start_command()
466 struct fdt_nand *config, u32 *reg_val) in set_bus_width_page_size() argument
469 *reg_val = CFG_BUS_WIDTH_8BIT; in set_bus_width_page_size()
471 *reg_val = CFG_BUS_WIDTH_16BIT; in set_bus_width_page_size()
479 *reg_val |= CFG_PAGE_SIZE_512; in set_bus_width_page_size()
481 *reg_val |= CFG_PAGE_SIZE_2048; in set_bus_width_page_size()
483 *reg_val |= CFG_PAGE_SIZE_4096; in set_bus_width_page_size()
508 u32 reg_val; in nand_rw_page() local
526 if (set_bus_width_page_size(mtd, config, ®_val)) in nand_rw_page()
550 reg_val |= (CFG_SKIP_SPARE_SEL_4 in nand_rw_page()
565 reg_val |= (CFG_SKIP_SPARE_DISABLE in nand_rw_page()
573 writel(reg_val, &info->reg->config); in nand_rw_page()
580 reg_val = CMD_CLE | CMD_ALE in nand_rw_page()
588 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); in nand_rw_page()
590 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); in nand_rw_page()
591 writel(reg_val, &info->reg->command); in nand_rw_page()
594 reg_val = DMA_MST_CTRL_GO_ENABLE in nand_rw_page()
600 reg_val |= DMA_MST_CTRL_DIR_READ; in nand_rw_page()
602 reg_val |= DMA_MST_CTRL_DIR_WRITE; in nand_rw_page()
604 writel(reg_val, &info->reg->dma_mst_ctrl); in nand_rw_page()
630 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf, in nand_rw_page()
634 if (reg_val & ECC_TAG_ERROR) in nand_rw_page()
636 if (reg_val & ECC_DATA_ERROR) in nand_rw_page()
639 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR)) in nand_rw_page()
724 u32 reg_val; in nand_rw_oob() local
734 if (set_bus_width_page_size(mtd, &info->config, ®_val)) in nand_rw_oob()
742 reg_val |= CFG_ECC_EN_TAG_ENABLE; in nand_rw_oob()
744 reg_val |= (CFG_ECC_EN_TAG_DISABLE); in nand_rw_oob()
746 reg_val |= ((tag_size - 1) | in nand_rw_oob()
750 writel(reg_val, &info->reg->config); in nand_rw_oob()
770 reg_val = CMD_CLE | CMD_ALE in nand_rw_oob()
776 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); in nand_rw_oob()
778 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); in nand_rw_oob()
779 writel(reg_val, &info->reg->command); in nand_rw_oob()
782 reg_val = DMA_MST_CTRL_GO_ENABLE in nand_rw_oob()
786 reg_val |= DMA_MST_CTRL_DIR_READ; in nand_rw_oob()
788 reg_val |= DMA_MST_CTRL_DIR_WRITE; in nand_rw_oob()
790 writel(reg_val, &info->reg->dma_mst_ctrl); in nand_rw_oob()
805 reg_val = (u32)check_ecc_error(info->reg, 0, 0, in nand_rw_oob()
808 if (reg_val & ECC_TAG_ERROR) in nand_rw_oob()
856 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
861 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
863 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
867 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) & in setup_timing()
869 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
873 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) & in setup_timing()
875 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
877 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
879 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
881 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
883 writel(reg_val, ®->timing); in setup_timing()
885 reg_val = 0; in setup_timing()
888 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK; in setup_timing()
889 writel(reg_val, ®->timing2); in setup_timing()