1226 	u32 min_clk_period = 0;  in sunxi_nand_chip_set_timings()  local
1230 	if (timings->tCLS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1231 		min_clk_period = timings->tCLS_min;  in sunxi_nand_chip_set_timings()
1234 	if (timings->tCLH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1235 		min_clk_period = timings->tCLH_min;  in sunxi_nand_chip_set_timings()
1238 	if (timings->tCS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1239 		min_clk_period = timings->tCS_min;  in sunxi_nand_chip_set_timings()
1242 	if (timings->tCH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1243 		min_clk_period = timings->tCH_min;  in sunxi_nand_chip_set_timings()
1246 	if (timings->tWP_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1247 		min_clk_period = timings->tWP_min;  in sunxi_nand_chip_set_timings()
1250 	if (timings->tWH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1251 		min_clk_period = timings->tWH_min;  in sunxi_nand_chip_set_timings()
1254 	if (timings->tALS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1255 		min_clk_period = timings->tALS_min;  in sunxi_nand_chip_set_timings()
1258 	if (timings->tDS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1259 		min_clk_period = timings->tDS_min;  in sunxi_nand_chip_set_timings()
1262 	if (timings->tDH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1263 		min_clk_period = timings->tDH_min;  in sunxi_nand_chip_set_timings()
1266 	if (timings->tRR_min > (min_clk_period * 3))  in sunxi_nand_chip_set_timings()
1267 		min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);  in sunxi_nand_chip_set_timings()
1270 	if (timings->tALH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1271 		min_clk_period = timings->tALH_min;  in sunxi_nand_chip_set_timings()
1274 	if (timings->tRP_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1275 		min_clk_period = timings->tRP_min;  in sunxi_nand_chip_set_timings()
1278 	if (timings->tREH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
1279 		min_clk_period = timings->tREH_min;  in sunxi_nand_chip_set_timings()
1282 	if (timings->tRC_min > (min_clk_period * 2))  in sunxi_nand_chip_set_timings()
1283 		min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);  in sunxi_nand_chip_set_timings()
1286 	if (timings->tWC_min > (min_clk_period * 2))  in sunxi_nand_chip_set_timings()
1287 		min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);  in sunxi_nand_chip_set_timings()
1291 					min_clk_period);  in sunxi_nand_chip_set_timings()
1297 	tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;  in sunxi_nand_chip_set_timings()
1303 	tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;  in sunxi_nand_chip_set_timings()
1310 					min_clk_period);  in sunxi_nand_chip_set_timings()
1333 	min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);  in sunxi_nand_chip_set_timings()
1341 	chip->clk_rate = 1000000000L / min_clk_period;  in sunxi_nand_chip_set_timings()