Lines Matching refs:ns2cycle
412 #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) macro
427 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | in pxa3xx_nand_set_timing()
428 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | in pxa3xx_nand_set_timing()
429 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | in pxa3xx_nand_set_timing()
430 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | in pxa3xx_nand_set_timing()
431 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | in pxa3xx_nand_set_timing()
432 NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); in pxa3xx_nand_set_timing()
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
435 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | in pxa3xx_nand_set_timing()
436 NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); in pxa3xx_nand_set_timing()
466 ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
467 NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
468 NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
469 NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
470 NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
471 NDTR0_tRP(ns2cycle(tRP_min, nand_clk)); in pxa3xx_nand_set_sdr_timing()
473 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
474 NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
475 NDTR1_tAR(ns2cycle(tAR_min, nand_clk)); in pxa3xx_nand_set_sdr_timing()