Lines Matching +full:pxa3xx +full:- +full:nand +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/mtd/nand/raw/pxa3xx_nand.c
12 #include <nand.h>
117 * by the controller (see NDCR_RD_ID_CNT_MASK).
123 writel((val), (info)->mmio_base + (off))
126 readl((info)->mmio_base + (off))
131 ERR_DMABUSERR = -1,
132 ERR_SENDCMD = -2,
133 ERR_UNCORERR = -3,
134 ERR_BBERR = -4,
135 ERR_CORERR = -5,
170 struct nand_hw_control controller; member
277 * dfc_width Width of flash controller(DWIDTH_C)
279 * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
411 /* convert nano-seconds to nand flash controller clock cycles */
423 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_timing()
427 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | in pxa3xx_nand_set_timing()
428 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | in pxa3xx_nand_set_timing()
429 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | in pxa3xx_nand_set_timing()
430 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | in pxa3xx_nand_set_timing()
431 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | in pxa3xx_nand_set_timing()
432 NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); in pxa3xx_nand_set_timing()
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
435 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | in pxa3xx_nand_set_timing()
436 NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); in pxa3xx_nand_set_timing()
438 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_timing()
439 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_timing()
447 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_sdr_timing()
448 struct nand_chip *chip = &host->chip; in pxa3xx_nand_set_sdr_timing()
452 u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000); in pxa3xx_nand_set_sdr_timing()
453 u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000); in pxa3xx_nand_set_sdr_timing()
454 u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000); in pxa3xx_nand_set_sdr_timing()
455 u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000); in pxa3xx_nand_set_sdr_timing()
456 u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000); in pxa3xx_nand_set_sdr_timing()
457 u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000); in pxa3xx_nand_set_sdr_timing()
458 u32 tR = chip->chip_delay * 1000; in pxa3xx_nand_set_sdr_timing()
459 u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000); in pxa3xx_nand_set_sdr_timing()
460 u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000); in pxa3xx_nand_set_sdr_timing()
477 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_sdr_timing()
478 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_sdr_timing()
486 struct nand_chip *chip = &host->chip; in pxa3xx_nand_init_timings()
487 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_init_timings()
489 struct mtd_info *mtd = nand_to_mtd(&host->chip); in pxa3xx_nand_init_timings()
496 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); in pxa3xx_nand_init_timings()
498 id = chip->read_byte(mtd); in pxa3xx_nand_init_timings()
499 id |= chip->read_byte(mtd) << 0x8; in pxa3xx_nand_init_timings()
504 if (f->chip_id == id) in pxa3xx_nand_init_timings()
509 dev_err(&info->pdev->dev, "Error: timings not found\n"); in pxa3xx_nand_init_timings()
510 return -EINVAL; in pxa3xx_nand_init_timings()
513 pxa3xx_nand_set_timing(host, f->timing); in pxa3xx_nand_init_timings()
515 if (f->flash_width == 16) { in pxa3xx_nand_init_timings()
516 info->reg_ndcr |= NDCR_DWIDTH_M; in pxa3xx_nand_init_timings()
517 chip->options |= NAND_BUSWIDTH_16; in pxa3xx_nand_init_timings()
520 info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; in pxa3xx_nand_init_timings()
522 mode = fls(mode) - 1; in pxa3xx_nand_init_timings()
546 ndcr = info->reg_ndcr; in pxa3xx_nand_start()
548 if (info->use_ecc) { in pxa3xx_nand_start()
550 if (info->ecc_bch) in pxa3xx_nand_start()
554 if (info->ecc_bch) in pxa3xx_nand_start()
560 if (info->use_spare) in pxa3xx_nand_start()
583 if (info->ecc_bch && !info->force_raw) { in drain_fifo()
595 readsl(info->mmio_base + NDDB, data, 8); in drain_fifo()
600 dev_err(&info->pdev->dev, in drain_fifo()
607 len -= 8; in drain_fifo()
611 readsl(info->mmio_base + NDDB, data, len); in drain_fifo()
616 int data_len = info->step_chunk_size; in handle_data_pio()
620 * consumed by the controller in the data section. Do not reorganize in handle_data_pio()
621 * here, do it in the ->read_page_raw() handler instead. in handle_data_pio()
623 if (info->force_raw) in handle_data_pio()
624 data_len += info->step_spare_size + info->ecc_size; in handle_data_pio()
626 switch (info->state) { in handle_data_pio()
628 if (info->step_chunk_size) in handle_data_pio()
629 writesl(info->mmio_base + NDDB, in handle_data_pio()
630 info->data_buff + info->data_buff_pos, in handle_data_pio()
633 if (info->step_spare_size) in handle_data_pio()
634 writesl(info->mmio_base + NDDB, in handle_data_pio()
635 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
636 DIV_ROUND_UP(info->step_spare_size, 4)); in handle_data_pio()
639 if (info->step_chunk_size) in handle_data_pio()
641 info->data_buff + info->data_buff_pos, in handle_data_pio()
644 if (info->force_raw) in handle_data_pio()
647 if (info->step_spare_size) in handle_data_pio()
649 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
650 DIV_ROUND_UP(info->step_spare_size, 4)); in handle_data_pio()
653 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, in handle_data_pio()
654 info->state); in handle_data_pio()
658 /* Update buffer pointers for multi-page read/write */ in handle_data_pio()
659 info->data_buff_pos += data_len; in handle_data_pio()
660 info->oob_buff_pos += info->step_spare_size; in handle_data_pio()
667 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq_thread()
677 if (info->cs == 0) { in pxa3xx_nand_irq()
685 /* TODO - find out why we need the delay during write operation. */ in pxa3xx_nand_irq()
691 info->retcode = ERR_UNCORERR; in pxa3xx_nand_irq()
693 info->retcode = ERR_CORERR; in pxa3xx_nand_irq()
694 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 && in pxa3xx_nand_irq()
695 info->ecc_bch) in pxa3xx_nand_irq()
696 info->ecc_err_cnt = NDSR_ERR_CNT(status); in pxa3xx_nand_irq()
698 info->ecc_err_cnt = 1; in pxa3xx_nand_irq()
705 info->max_bitflips = max_t(unsigned int, in pxa3xx_nand_irq()
706 info->max_bitflips, in pxa3xx_nand_irq()
707 info->ecc_err_cnt); in pxa3xx_nand_irq()
710 info->state = (status & NDSR_RDDREQ) ? in pxa3xx_nand_irq()
712 /* Call the IRQ thread in U-Boot directly */ in pxa3xx_nand_irq()
717 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq()
721 info->state = STATE_READY; in pxa3xx_nand_irq()
728 * interrupt on its own. This lets the controller exit the IRQ in pxa3xx_nand_irq()
734 info->state = STATE_CMD_HANDLE; in pxa3xx_nand_irq()
737 * Command buffer registers NDCB{0-2} (and optionally NDCB3) in pxa3xx_nand_irq()
744 nand_writel(info, NDCB0, info->ndcb0); in pxa3xx_nand_irq()
745 nand_writel(info, NDCB0, info->ndcb1); in pxa3xx_nand_irq()
746 nand_writel(info, NDCB0, info->ndcb2); in pxa3xx_nand_irq()
749 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_irq()
750 nand_writel(info, NDCB0, info->ndcb3); in pxa3xx_nand_irq()
754 info->cmd_complete = 1; in pxa3xx_nand_irq()
756 info->dev_ready = 1; in pxa3xx_nand_irq()
763 for (; len > 0; len--) in is_buf_blank()
773 if (page_size < info->chunk_size) { in set_command_address()
774 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) in set_command_address()
777 info->ndcb2 = 0; in set_command_address()
779 info->ndcb1 = ((page_addr & 0xFFFF) << 16) in set_command_address()
783 info->ndcb2 = (page_addr & 0xFF0000) >> 16; in set_command_address()
785 info->ndcb2 = 0; in set_command_address()
791 struct pxa3xx_nand_host *host = info->host[info->cs]; in prepare_start_command()
792 struct mtd_info *mtd = nand_to_mtd(&host->chip); in prepare_start_command()
795 info->buf_start = 0; in prepare_start_command()
796 info->buf_count = 0; in prepare_start_command()
797 info->data_buff_pos = 0; in prepare_start_command()
798 info->oob_buff_pos = 0; in prepare_start_command()
799 info->step_chunk_size = 0; in prepare_start_command()
800 info->step_spare_size = 0; in prepare_start_command()
801 info->cur_chunk = 0; in prepare_start_command()
802 info->use_ecc = 0; in prepare_start_command()
803 info->use_spare = 1; in prepare_start_command()
804 info->retcode = ERR_NONE; in prepare_start_command()
805 info->ecc_err_cnt = 0; in prepare_start_command()
806 info->ndcb3 = 0; in prepare_start_command()
807 info->need_wait = 0; in prepare_start_command()
813 if (!info->force_raw) in prepare_start_command()
814 info->use_ecc = 1; in prepare_start_command()
817 info->use_spare = 0; in prepare_start_command()
820 info->ndcb1 = 0; in prepare_start_command()
821 info->ndcb2 = 0; in prepare_start_command()
832 info->buf_count = mtd->writesize + mtd->oobsize; in prepare_start_command()
833 memset(info->data_buff, 0xFF, info->buf_count); in prepare_start_command()
844 host = info->host[info->cs]; in prepare_set_command()
845 mtd = nand_to_mtd(&host->chip); in prepare_set_command()
849 if (info->cs != 0) in prepare_set_command()
850 info->ndcb0 = NDCB0_CSEL; in prepare_set_command()
852 info->ndcb0 = 0; in prepare_set_command()
857 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles in prepare_set_command()
858 + host->col_addr_cycles); in prepare_set_command()
863 info->buf_start = column; in prepare_set_command()
864 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
869 info->buf_start += mtd->writesize; in prepare_set_command()
871 if (info->cur_chunk < info->nfullchunks) { in prepare_set_command()
872 info->step_chunk_size = info->chunk_size; in prepare_set_command()
873 info->step_spare_size = info->spare_size; in prepare_set_command()
875 info->step_chunk_size = info->last_chunk_size; in prepare_set_command()
876 info->step_spare_size = info->last_spare_size; in prepare_set_command()
881 * which is either naked-read or last-read according to the in prepare_set_command()
884 if (info->force_raw) { in prepare_set_command()
885 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) | in prepare_set_command()
888 info->ndcb3 = info->step_chunk_size + in prepare_set_command()
889 info->step_spare_size + info->ecc_size; in prepare_set_command()
890 } else if (mtd->writesize == info->chunk_size) { in prepare_set_command()
891 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); in prepare_set_command()
892 } else if (mtd->writesize > info->chunk_size) { in prepare_set_command()
893 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) in prepare_set_command()
896 info->ndcb3 = info->step_chunk_size + in prepare_set_command()
897 info->step_spare_size; in prepare_set_command()
900 set_command_address(info, mtd->writesize, column, page_addr); in prepare_set_command()
905 info->buf_start = column; in prepare_set_command()
906 set_command_address(info, mtd->writesize, 0, page_addr); in prepare_set_command()
912 if (mtd->writesize > info->chunk_size) { in prepare_set_command()
913 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
922 if (is_buf_blank(info->data_buff, in prepare_set_command()
923 (mtd->writesize + mtd->oobsize))) { in prepare_set_command()
928 if (info->cur_chunk < info->nfullchunks) { in prepare_set_command()
929 info->step_chunk_size = info->chunk_size; in prepare_set_command()
930 info->step_spare_size = info->spare_size; in prepare_set_command()
932 info->step_chunk_size = info->last_chunk_size; in prepare_set_command()
933 info->step_spare_size = info->last_spare_size; in prepare_set_command()
937 if (mtd->writesize > info->chunk_size) { in prepare_set_command()
941 * or a naked-write depending on the current stage. in prepare_set_command()
943 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
946 info->ndcb3 = info->step_chunk_size + in prepare_set_command()
947 info->step_spare_size; in prepare_set_command()
953 if (info->cur_chunk == info->ntotalchunks) { in prepare_set_command()
954 info->ndcb0 = NDCB0_CMD_TYPE(0x1) in prepare_set_command()
957 info->ndcb1 = 0; in prepare_set_command()
958 info->ndcb2 = 0; in prepare_set_command()
959 info->ndcb3 = 0; in prepare_set_command()
962 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
973 info->buf_count = INIT_BUFFER_SIZE; in prepare_set_command()
974 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
978 info->ndcb1 = (column & 0xFF); in prepare_set_command()
979 info->ndcb3 = INIT_BUFFER_SIZE; in prepare_set_command()
980 info->step_chunk_size = INIT_BUFFER_SIZE; in prepare_set_command()
984 info->buf_count = READ_ID_BYTES; in prepare_set_command()
985 info->ndcb0 |= NDCB0_CMD_TYPE(3) in prepare_set_command()
988 info->ndcb1 = (column & 0xFF); in prepare_set_command()
990 info->step_chunk_size = 8; in prepare_set_command()
993 info->buf_count = 1; in prepare_set_command()
994 info->ndcb0 |= NDCB0_CMD_TYPE(4) in prepare_set_command()
998 info->step_chunk_size = 8; in prepare_set_command()
1002 info->ndcb0 |= NDCB0_CMD_TYPE(2) in prepare_set_command()
1008 info->ndcb1 = page_addr; in prepare_set_command()
1009 info->ndcb2 = 0; in prepare_set_command()
1013 info->ndcb0 |= NDCB0_CMD_TYPE(5) in prepare_set_command()
1024 dev_err(&info->pdev->dev, "non-supported command %x\n", in prepare_set_command()
1037 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc()
1043 * for indexing a word-oriented device in nand_cmdfunc()
1045 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc()
1049 * There may be different NAND chip hooked to in nand_cmdfunc()
1053 if (info->cs != host->cs) { in nand_cmdfunc()
1054 info->cs = host->cs; in nand_cmdfunc()
1055 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc()
1056 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc()
1061 info->state = STATE_PREPARED; in nand_cmdfunc()
1067 info->cmd_complete = 0; in nand_cmdfunc()
1068 info->dev_ready = 0; in nand_cmdfunc()
1069 info->need_wait = 1; in nand_cmdfunc()
1080 if (info->cmd_complete) in nand_cmdfunc()
1084 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); in nand_cmdfunc()
1089 info->state = STATE_IDLE; in nand_cmdfunc()
1098 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc_extended()
1104 * for indexing a word-oriented device in nand_cmdfunc_extended()
1106 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc_extended()
1110 * There may be different NAND chip hooked to in nand_cmdfunc_extended()
1114 if (info->cs != host->cs) { in nand_cmdfunc_extended()
1115 info->cs = host->cs; in nand_cmdfunc_extended()
1116 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc_extended()
1117 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc_extended()
1147 info->need_wait = 1; in nand_cmdfunc_extended()
1148 info->dev_ready = 0; in nand_cmdfunc_extended()
1153 info->state = STATE_PREPARED; in nand_cmdfunc_extended()
1157 info->need_wait = 0; in nand_cmdfunc_extended()
1158 info->dev_ready = 1; in nand_cmdfunc_extended()
1162 info->cmd_complete = 0; in nand_cmdfunc_extended()
1173 if (info->cmd_complete) in nand_cmdfunc_extended()
1177 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); in nand_cmdfunc_extended()
1188 info->cur_chunk++; in nand_cmdfunc_extended()
1191 if (info->cur_chunk == info->ntotalchunks && in nand_cmdfunc_extended()
1199 if (info->cur_chunk == (info->ntotalchunks + 1) && in nand_cmdfunc_extended()
1206 if (info->cur_chunk == info->ntotalchunks - 1) in nand_cmdfunc_extended()
1216 info->cur_chunk == info->ntotalchunks) { in nand_cmdfunc_extended()
1221 info->state = STATE_IDLE; in nand_cmdfunc_extended()
1228 chip->write_buf(mtd, buf, mtd->writesize); in pxa3xx_nand_write_page_hwecc()
1229 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); in pxa3xx_nand_write_page_hwecc()
1239 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_page_hwecc()
1242 chip->read_buf(mtd, buf, mtd->writesize); in pxa3xx_nand_read_page_hwecc()
1243 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); in pxa3xx_nand_read_page_hwecc()
1245 if (info->retcode == ERR_CORERR && info->use_ecc) { in pxa3xx_nand_read_page_hwecc()
1246 mtd->ecc_stats.corrected += info->ecc_err_cnt; in pxa3xx_nand_read_page_hwecc()
1248 } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) { in pxa3xx_nand_read_page_hwecc()
1250 * Empty pages will trigger uncorrectable errors. Re-read the in pxa3xx_nand_read_page_hwecc()
1255 chip->ecc.read_page_raw(mtd, chip, buf, oob_required, page); in pxa3xx_nand_read_page_hwecc()
1256 bf = nand_check_erased_ecc_chunk(buf, mtd->writesize, in pxa3xx_nand_read_page_hwecc()
1257 chip->oob_poi, mtd->oobsize, in pxa3xx_nand_read_page_hwecc()
1258 NULL, 0, chip->ecc.strength); in pxa3xx_nand_read_page_hwecc()
1260 mtd->ecc_stats.failed++; in pxa3xx_nand_read_page_hwecc()
1262 mtd->ecc_stats.corrected += bf; in pxa3xx_nand_read_page_hwecc()
1263 info->max_bitflips = max_t(unsigned int, in pxa3xx_nand_read_page_hwecc()
1264 info->max_bitflips, bf); in pxa3xx_nand_read_page_hwecc()
1265 info->retcode = ERR_CORERR; in pxa3xx_nand_read_page_hwecc()
1267 info->retcode = ERR_NONE; in pxa3xx_nand_read_page_hwecc()
1270 } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) { in pxa3xx_nand_read_page_hwecc()
1272 if (is_buf_blank(buf, mtd->writesize)) in pxa3xx_nand_read_page_hwecc()
1273 info->retcode = ERR_NONE; in pxa3xx_nand_read_page_hwecc()
1275 mtd->ecc_stats.failed++; in pxa3xx_nand_read_page_hwecc()
1278 return info->max_bitflips; in pxa3xx_nand_read_page_hwecc()
1285 struct pxa3xx_nand_host *host = chip->priv; in pxa3xx_nand_read_page_raw()
1286 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_page_raw()
1289 if (!info->ecc_bch) in pxa3xx_nand_read_page_raw()
1290 return -ENOTSUPP; in pxa3xx_nand_read_page_raw()
1293 * Set the force_raw boolean, then re-call ->cmdfunc() that will run in pxa3xx_nand_read_page_raw()
1296 info->force_raw = true; in pxa3xx_nand_read_page_raw()
1297 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); in pxa3xx_nand_read_page_raw()
1299 ecc_off_buf = (info->nfullchunks * info->spare_size) + in pxa3xx_nand_read_page_raw()
1300 info->last_spare_size; in pxa3xx_nand_read_page_raw()
1301 for (chunk = 0; chunk < info->nfullchunks; chunk++) { in pxa3xx_nand_read_page_raw()
1302 chip->read_buf(mtd, in pxa3xx_nand_read_page_raw()
1303 buf + (chunk * info->chunk_size), in pxa3xx_nand_read_page_raw()
1304 info->chunk_size); in pxa3xx_nand_read_page_raw()
1305 chip->read_buf(mtd, in pxa3xx_nand_read_page_raw()
1306 chip->oob_poi + in pxa3xx_nand_read_page_raw()
1307 (chunk * (info->spare_size)), in pxa3xx_nand_read_page_raw()
1308 info->spare_size); in pxa3xx_nand_read_page_raw()
1309 chip->read_buf(mtd, in pxa3xx_nand_read_page_raw()
1310 chip->oob_poi + ecc_off_buf + in pxa3xx_nand_read_page_raw()
1311 (chunk * (info->ecc_size)), in pxa3xx_nand_read_page_raw()
1312 info->ecc_size - 2); in pxa3xx_nand_read_page_raw()
1315 if (info->ntotalchunks > info->nfullchunks) { in pxa3xx_nand_read_page_raw()
1316 chip->read_buf(mtd, in pxa3xx_nand_read_page_raw()
1317 buf + (info->nfullchunks * info->chunk_size), in pxa3xx_nand_read_page_raw()
1318 info->last_chunk_size); in pxa3xx_nand_read_page_raw()
1319 chip->read_buf(mtd, in pxa3xx_nand_read_page_raw()
1320 chip->oob_poi + in pxa3xx_nand_read_page_raw()
1321 (info->nfullchunks * (info->spare_size)), in pxa3xx_nand_read_page_raw()
1322 info->last_spare_size); in pxa3xx_nand_read_page_raw()
1323 chip->read_buf(mtd, in pxa3xx_nand_read_page_raw()
1324 chip->oob_poi + ecc_off_buf + in pxa3xx_nand_read_page_raw()
1325 (info->nfullchunks * (info->ecc_size)), in pxa3xx_nand_read_page_raw()
1326 info->ecc_size - 2); in pxa3xx_nand_read_page_raw()
1329 info->force_raw = false; in pxa3xx_nand_read_page_raw()
1338 chip->pagebuf = -1; in pxa3xx_nand_read_oob_raw()
1340 return chip->ecc.read_page_raw(mtd, chip, chip->buffers->databuf, true, in pxa3xx_nand_read_oob_raw()
1348 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_byte()
1351 if (info->buf_start < info->buf_count) in pxa3xx_nand_read_byte()
1353 retval = info->data_buff[info->buf_start++]; in pxa3xx_nand_read_byte()
1362 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_word()
1365 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { in pxa3xx_nand_read_word()
1366 retval = *((u16 *)(info->data_buff+info->buf_start)); in pxa3xx_nand_read_word()
1367 info->buf_start += 2; in pxa3xx_nand_read_word()
1376 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_buf()
1377 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_read_buf()
1379 memcpy(buf, info->data_buff + info->buf_start, real_len); in pxa3xx_nand_read_buf()
1380 info->buf_start += real_len; in pxa3xx_nand_read_buf()
1388 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_write_buf()
1389 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_write_buf()
1391 memcpy(info->data_buff + info->buf_start, buf, real_len); in pxa3xx_nand_write_buf()
1392 info->buf_start += real_len; in pxa3xx_nand_write_buf()
1404 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_waitfunc()
1406 if (info->need_wait) { in pxa3xx_nand_waitfunc()
1409 info->need_wait = 0; in pxa3xx_nand_waitfunc()
1419 if (info->dev_ready) in pxa3xx_nand_waitfunc()
1423 dev_err(&info->pdev->dev, "Ready timeout!!!\n"); in pxa3xx_nand_waitfunc()
1430 if (this->state == FL_WRITING || this->state == FL_ERASING) { in pxa3xx_nand_waitfunc()
1431 if (info->retcode == ERR_NONE) in pxa3xx_nand_waitfunc()
1442 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_config_ident()
1445 info->reg_ndcr = 0x0; /* enable all interrupts */ in pxa3xx_nand_config_ident()
1446 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_config_ident()
1447 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); in pxa3xx_nand_config_ident()
1448 info->reg_ndcr |= NDCR_SPARE_EN; in pxa3xx_nand_config_ident()
1455 struct pxa3xx_nand_host *host = info->host[info->cs]; in pxa3xx_nand_config_tail()
1456 struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip); in pxa3xx_nand_config_tail()
1459 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; in pxa3xx_nand_config_tail()
1460 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0; in pxa3xx_nand_config_tail()
1461 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0; in pxa3xx_nand_config_tail()
1466 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_detect_config()
1470 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; in pxa3xx_nand_detect_config()
1471 info->reg_ndcr = ndcr & in pxa3xx_nand_detect_config()
1473 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_detect_config()
1474 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); in pxa3xx_nand_detect_config()
1475 info->ndtr1cs0 = nand_readl(info, NDTR1CS0); in pxa3xx_nand_detect_config()
1480 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in pxa3xx_nand_init_buff()
1481 if (info->data_buff == NULL) in pxa3xx_nand_init_buff()
1482 return -ENOMEM; in pxa3xx_nand_init_buff()
1488 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_sensing()
1489 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_sensing()
1495 mtd = nand_to_mtd(&info->host[info->cs]->chip); in pxa3xx_nand_sensing()
1499 info->reg_ndcr = 0x0; /* enable all interrupts */ in pxa3xx_nand_sensing()
1500 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_sensing()
1501 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); in pxa3xx_nand_sensing()
1502 info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */ in pxa3xx_nand_sensing()
1511 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0); in pxa3xx_nand_sensing()
1512 ret = chip->waitfunc(mtd, chip); in pxa3xx_nand_sensing()
1514 return -ENODEV; in pxa3xx_nand_sensing()
1524 info->nfullchunks = 1; in pxa_ecc_init()
1525 info->ntotalchunks = 1; in pxa_ecc_init()
1526 info->chunk_size = 2048; in pxa_ecc_init()
1527 info->spare_size = 40; in pxa_ecc_init()
1528 info->ecc_size = 24; in pxa_ecc_init()
1529 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1530 ecc->size = 512; in pxa_ecc_init()
1531 ecc->strength = 1; in pxa_ecc_init()
1534 info->nfullchunks = 1; in pxa_ecc_init()
1535 info->ntotalchunks = 1; in pxa_ecc_init()
1536 info->chunk_size = 512; in pxa_ecc_init()
1537 info->spare_size = 8; in pxa_ecc_init()
1538 info->ecc_size = 8; in pxa_ecc_init()
1539 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1540 ecc->size = 512; in pxa_ecc_init()
1541 ecc->strength = 1; in pxa_ecc_init()
1544 * Required ECC: 4-bit correction per 512 bytes in pxa_ecc_init()
1545 * Select: 16-bit correction per 2048 bytes in pxa_ecc_init()
1548 info->ecc_bch = 1; in pxa_ecc_init()
1549 info->nfullchunks = 1; in pxa_ecc_init()
1550 info->ntotalchunks = 1; in pxa_ecc_init()
1551 info->chunk_size = 2048; in pxa_ecc_init()
1552 info->spare_size = 32; in pxa_ecc_init()
1553 info->ecc_size = 32; in pxa_ecc_init()
1554 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1555 ecc->size = info->chunk_size; in pxa_ecc_init()
1556 ecc->layout = &ecc_layout_2KB_bch4bit; in pxa_ecc_init()
1557 ecc->strength = 16; in pxa_ecc_init()
1560 info->ecc_bch = 1; in pxa_ecc_init()
1561 info->nfullchunks = 2; in pxa_ecc_init()
1562 info->ntotalchunks = 2; in pxa_ecc_init()
1563 info->chunk_size = 2048; in pxa_ecc_init()
1564 info->spare_size = 32; in pxa_ecc_init()
1565 info->ecc_size = 32; in pxa_ecc_init()
1566 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1567 ecc->size = info->chunk_size; in pxa_ecc_init()
1568 ecc->layout = &ecc_layout_4KB_bch4bit; in pxa_ecc_init()
1569 ecc->strength = 16; in pxa_ecc_init()
1572 info->ecc_bch = 1; in pxa_ecc_init()
1573 info->nfullchunks = 4; in pxa_ecc_init()
1574 info->ntotalchunks = 4; in pxa_ecc_init()
1575 info->chunk_size = 2048; in pxa_ecc_init()
1576 info->spare_size = 32; in pxa_ecc_init()
1577 info->ecc_size = 32; in pxa_ecc_init()
1578 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1579 ecc->size = info->chunk_size; in pxa_ecc_init()
1580 ecc->layout = &ecc_layout_8KB_bch4bit; in pxa_ecc_init()
1581 ecc->strength = 16; in pxa_ecc_init()
1584 * Required ECC: 8-bit correction per 512 bytes in pxa_ecc_init()
1585 * Select: 16-bit correction per 1024 bytes in pxa_ecc_init()
1588 info->ecc_bch = 1; in pxa_ecc_init()
1589 info->nfullchunks = 1; in pxa_ecc_init()
1590 info->ntotalchunks = 2; in pxa_ecc_init()
1591 info->chunk_size = 1024; in pxa_ecc_init()
1592 info->spare_size = 0; in pxa_ecc_init()
1593 info->last_chunk_size = 1024; in pxa_ecc_init()
1594 info->last_spare_size = 32; in pxa_ecc_init()
1595 info->ecc_size = 32; in pxa_ecc_init()
1596 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1597 ecc->size = info->chunk_size; in pxa_ecc_init()
1598 ecc->layout = &ecc_layout_2KB_bch8bit; in pxa_ecc_init()
1599 ecc->strength = 16; in pxa_ecc_init()
1602 info->ecc_bch = 1; in pxa_ecc_init()
1603 info->nfullchunks = 4; in pxa_ecc_init()
1604 info->ntotalchunks = 5; in pxa_ecc_init()
1605 info->chunk_size = 1024; in pxa_ecc_init()
1606 info->spare_size = 0; in pxa_ecc_init()
1607 info->last_chunk_size = 0; in pxa_ecc_init()
1608 info->last_spare_size = 64; in pxa_ecc_init()
1609 info->ecc_size = 32; in pxa_ecc_init()
1610 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1611 ecc->size = info->chunk_size; in pxa_ecc_init()
1612 ecc->layout = &ecc_layout_4KB_bch8bit; in pxa_ecc_init()
1613 ecc->strength = 16; in pxa_ecc_init()
1616 info->ecc_bch = 1; in pxa_ecc_init()
1617 info->nfullchunks = 8; in pxa_ecc_init()
1618 info->ntotalchunks = 9; in pxa_ecc_init()
1619 info->chunk_size = 1024; in pxa_ecc_init()
1620 info->spare_size = 0; in pxa_ecc_init()
1621 info->last_chunk_size = 0; in pxa_ecc_init()
1622 info->last_spare_size = 160; in pxa_ecc_init()
1623 info->ecc_size = 32; in pxa_ecc_init()
1624 ecc->mode = NAND_ECC_HW; in pxa_ecc_init()
1625 ecc->size = info->chunk_size; in pxa_ecc_init()
1626 ecc->layout = &ecc_layout_8KB_bch8bit; in pxa_ecc_init()
1627 ecc->strength = 16; in pxa_ecc_init()
1630 dev_err(&info->pdev->dev, in pxa_ecc_init()
1633 return -ENODEV; in pxa_ecc_init()
1643 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_scan()
1644 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_scan()
1648 if (pdata->keep_config) { in pxa3xx_nand_scan()
1656 dev_info(&info->pdev->dev, in pxa3xx_nand_scan()
1658 info->cs); in pxa3xx_nand_scan()
1664 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_scan()
1668 return -ENODEV; in pxa3xx_nand_scan()
1670 if (!pdata->keep_config) { in pxa3xx_nand_scan()
1673 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1681 * We'll use a bad block table stored in-flash and don't in pxa3xx_nand_scan()
1684 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM; in pxa3xx_nand_scan()
1685 chip->bbt_td = &bbt_main_descr; in pxa3xx_nand_scan()
1686 chip->bbt_md = &bbt_mirror_descr; in pxa3xx_nand_scan()
1689 if (pdata->ecc_strength && pdata->ecc_step_size) { in pxa3xx_nand_scan()
1690 ecc_strength = pdata->ecc_strength; in pxa3xx_nand_scan()
1691 ecc_step = pdata->ecc_step_size; in pxa3xx_nand_scan()
1693 ecc_strength = chip->ecc_strength_ds; in pxa3xx_nand_scan()
1694 ecc_step = chip->ecc_step_ds; in pxa3xx_nand_scan()
1697 /* Set default ECC strength requirements on non-ONFI devices */ in pxa3xx_nand_scan()
1703 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, in pxa3xx_nand_scan()
1704 ecc_step, mtd->writesize); in pxa3xx_nand_scan()
1713 if (mtd->writesize > info->chunk_size) { in pxa3xx_nand_scan()
1714 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) { in pxa3xx_nand_scan()
1715 chip->cmdfunc = nand_cmdfunc_extended; in pxa3xx_nand_scan()
1717 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1719 return -ENODEV; in pxa3xx_nand_scan()
1724 if (mtd->writesize >= 2048) in pxa3xx_nand_scan()
1725 host->col_addr_cycles = 2; in pxa3xx_nand_scan()
1727 host->col_addr_cycles = 1; in pxa3xx_nand_scan()
1730 kfree(info->data_buff); in pxa3xx_nand_scan()
1733 info->buf_size = mtd->writesize + mtd->oobsize; in pxa3xx_nand_scan()
1737 info->oob_buff = info->data_buff + mtd->writesize; in pxa3xx_nand_scan()
1739 if ((mtd->size >> chip->page_shift) > 65536) in pxa3xx_nand_scan()
1740 host->row_addr_cycles = 3; in pxa3xx_nand_scan()
1742 host->row_addr_cycles = 2; in pxa3xx_nand_scan()
1744 if (!pdata->keep_config) in pxa3xx_nand_scan()
1758 pdata = info->pdata; in alloc_nand_resource()
1759 if (pdata->num_cs <= 0) in alloc_nand_resource()
1760 return -ENODEV; in alloc_nand_resource()
1762 info->variant = pxa3xx_nand_get_variant(); in alloc_nand_resource()
1763 for (cs = 0; cs < pdata->num_cs; cs++) { in alloc_nand_resource()
1768 info->host[cs] = host; in alloc_nand_resource()
1769 host->cs = cs; in alloc_nand_resource()
1770 host->info_data = info; in alloc_nand_resource()
1771 mtd->owner = THIS_MODULE; in alloc_nand_resource()
1774 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; in alloc_nand_resource()
1775 chip->ecc.read_page_raw = pxa3xx_nand_read_page_raw; in alloc_nand_resource()
1776 chip->ecc.read_oob_raw = pxa3xx_nand_read_oob_raw; in alloc_nand_resource()
1777 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; in alloc_nand_resource()
1778 chip->controller = &info->controller; in alloc_nand_resource()
1779 chip->waitfunc = pxa3xx_nand_waitfunc; in alloc_nand_resource()
1780 chip->select_chip = pxa3xx_nand_select_chip; in alloc_nand_resource()
1781 chip->read_word = pxa3xx_nand_read_word; in alloc_nand_resource()
1782 chip->read_byte = pxa3xx_nand_read_byte; in alloc_nand_resource()
1783 chip->read_buf = pxa3xx_nand_read_buf; in alloc_nand_resource()
1784 chip->write_buf = pxa3xx_nand_write_buf; in alloc_nand_resource()
1785 chip->options |= NAND_NO_SUBPAGE_WRITE; in alloc_nand_resource()
1786 chip->cmdfunc = nand_cmdfunc; in alloc_nand_resource()
1790 info->buf_size = INIT_BUFFER_SIZE; in alloc_nand_resource()
1791 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in alloc_nand_resource()
1792 if (info->data_buff == NULL) { in alloc_nand_resource()
1793 ret = -ENOMEM; in alloc_nand_resource()
1802 kfree(info->data_buff); in alloc_nand_resource()
1810 const void *blob = gd->fdt_blob; in pxa3xx_nand_probe_dt()
1811 int node = -1; in pxa3xx_nand_probe_dt()
1815 return -ENOMEM; in pxa3xx_nand_probe_dt()
1820 "marvell,mvebu-pxa3xx-nand"); in pxa3xx_nand_probe_dt()
1828 /* Get the first enabled NAND controler base address */ in pxa3xx_nand_probe_dt()
1829 info->mmio_base = in pxa3xx_nand_probe_dt()
1833 pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1); in pxa3xx_nand_probe_dt()
1834 if (pdata->num_cs != 1) { in pxa3xx_nand_probe_dt()
1835 pr_err("pxa3xx driver supports single CS only\n"); in pxa3xx_nand_probe_dt()
1839 if (fdtdec_get_bool(blob, node, "nand-enable-arbiter")) in pxa3xx_nand_probe_dt()
1840 pdata->enable_arbiter = 1; in pxa3xx_nand_probe_dt()
1842 if (fdtdec_get_bool(blob, node, "nand-keep-config")) in pxa3xx_nand_probe_dt()
1843 pdata->keep_config = 1; in pxa3xx_nand_probe_dt()
1851 pdata->ecc_strength = fdtdec_get_int(blob, node, in pxa3xx_nand_probe_dt()
1852 "nand-ecc-strength", 0); in pxa3xx_nand_probe_dt()
1855 pdata->ecc_step_size = fdtdec_get_int(blob, node, in pxa3xx_nand_probe_dt()
1856 "nand-ecc-step-size", 0); in pxa3xx_nand_probe_dt()
1858 info->pdata = pdata; in pxa3xx_nand_probe_dt()
1860 /* Currently support only a single NAND controller */ in pxa3xx_nand_probe_dt()
1865 return -EINVAL; in pxa3xx_nand_probe_dt()
1877 pdata = info->pdata; in pxa3xx_nand_probe()
1881 dev_err(&pdev->dev, "alloc nand resource failed\n"); in pxa3xx_nand_probe()
1886 for (cs = 0; cs < pdata->num_cs; cs++) { in pxa3xx_nand_probe()
1887 struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip); in pxa3xx_nand_probe()
1894 mtd->name = "pxa3xx_nand-0"; in pxa3xx_nand_probe()
1895 info->cs = cs; in pxa3xx_nand_probe()
1898 dev_info(&pdev->dev, "failed to scan nand at cs %d\n", in pxa3xx_nand_probe()
1910 return -ENODEV; in pxa3xx_nand_probe()