1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2004-2007 Freescale Semiconductor, Inc.
14 #include <asm/arch/imx-regs.h>
103 	while (size--)  in mxc_nand_memcpy32()
117 	while (max_retries-- > 0) {
119 		tmp = readnfc(&host->regs->config2);
122 			writenfc(tmp, &host->regs->config2);
124 		tmp = readnfc(&host->ip_regs->ipc);
127 			writenfc(tmp, &host->ip_regs->ipc);
147 	writenfc(cmd, &host->regs->flash_cmd);
148 	writenfc(NFC_CMD, &host->regs->operation);
163 	writenfc(addr, &host->regs->flash_addr);
164 	writenfc(NFC_ADDR, &host->regs->operation);
172  * of data currently in the NANDFC RAM buffer to the NAND device.
189 			void __iomem *src = &host->regs->spare_area[0][i * 16];
190 			void __iomem *dst = &host->regs->spare_area[i][0];
197 	writenfc(buf_id, &host->regs->buf_addr);
199 	uint32_t tmp = readnfc(&host->regs->config1);
202 	writenfc(tmp, &host->regs->config1);
206 	if (!host->pagesize_2k) {
207 		uint32_t config1 = readnfc(&host->regs->config1);
212 		writenfc(config1, &host->regs->config1);
215 	writenfc(NFC_INPUT, &host->regs->operation);
223  * NAND device into in the NANDFC ram buffer.
231 	writenfc(buf_id, &host->regs->buf_addr);
233 	uint32_t tmp = readnfc(&host->regs->config1);
236 	writenfc(tmp, &host->regs->config1);
240 	if (!host->pagesize_2k) {
241 		uint32_t config1 = readnfc(&host->regs->config1);
246 		writenfc(config1, &host->regs->config1);
249 	writenfc(NFC_OUTPUT, &host->regs->operation);
263 			void __iomem *src = &host->regs->spare_area[i][0];
264 			void __iomem *dst = &host->regs->spare_area[0][i * 16];
278 	writenfc(0x0, &host->regs->buf_addr);
280 	tmp = readnfc(&host->regs->config1);
282 	writenfc(tmp, &host->regs->config1);
286 	tmp = readnfc(&host->regs->config1);
288 	writenfc(tmp, &host->regs->config1);
290 	writenfc(NFC_ID, &host->regs->operation);
303 	void __iomem *main_buf = host->regs->main_area[1];
313 	writenfc(1, &host->regs->buf_addr);
317 	tmp = readnfc(&host->regs->config1);
319 	writenfc(tmp, &host->regs->config1);
321 	writenfc(NFC_STATUS, &host->regs->operation);
334 	ret = readnfc(&host->regs->config1) >> 16;
341 static int mxc_nand_dev_ready(struct mtd_info *mtd)  argument
350 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)  argument
352 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
355 	uint16_t tmp = readnfc(&host->regs->config1);
361 	writenfc(tmp, &host->regs->config1);
363 	uint32_t tmp = readnfc(&host->ip_regs->config2);
369 	writenfc(tmp, &host->ip_regs->config2);
374 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)  argument
383 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,  argument
388 	uint8_t *buf = chip->oob_poi;
389 	int length = mtd->oobsize;
390 	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
397 	chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
398 	for (i = 0; i < chip->ecc.steps; i++) {
399 		toread = min_t(int, length, chip->ecc.prepad);
401 			chip->read_buf(mtd, bufpoi, toread);
403 			length -= toread;
405 		bufpoi += chip->ecc.bytes;
406 		host->col_addr += chip->ecc.bytes;
407 		length -= chip->ecc.bytes;
409 		toread = min_t(int, length, chip->ecc.postpad);
411 			chip->read_buf(mtd, bufpoi, toread);
413 			length -= toread;
417 		chip->read_buf(mtd, bufpoi, length);
419 	_mxc_nand_enable_hwecc(mtd, 0);
420 	chip->cmdfunc(mtd, NAND_CMD_READOOB,
421 			mtd->writesize + chip->ecc.prepad, page);
422 	bufpoi = buf + chip->ecc.prepad;
423 	length = mtd->oobsize - chip->ecc.prepad;
424 	for (i = 0; i < chip->ecc.steps; i++) {
425 		toread = min_t(int, length, chip->ecc.bytes);
426 		chip->read_buf(mtd, bufpoi, toread);
428 		length -= eccpitch;
429 		host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
431 	_mxc_nand_enable_hwecc(mtd, 1);
435 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,  argument
442 	int eccsize = chip->ecc.size;
443 	int eccbytes = chip->ecc.bytes;
444 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
445 	uint8_t *oob = chip->oob_poi;
449 	_mxc_nand_enable_hwecc(mtd, 0);
450 	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
452 	for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
453 		host->col_addr = n * eccsize;
454 		chip->read_buf(mtd, buf, eccsize);
457 		host->col_addr = mtd->writesize + n * eccpitch;
458 		if (chip->ecc.prepad) {
459 			chip->read_buf(mtd, oob, chip->ecc.prepad);
460 			oob += chip->ecc.prepad;
463 		chip->read_buf(mtd, oob, eccbytes);
466 		if (chip->ecc.postpad) {
467 			chip->read_buf(mtd, oob, chip->ecc.postpad);
468 			oob += chip->ecc.postpad;
472 	size = mtd->oobsize - (oob - chip->oob_poi);
474 		chip->read_buf(mtd, oob, size);
475 	_mxc_nand_enable_hwecc(mtd, 1);
480 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,  argument
487 	int n, eccsize = chip->ecc.size;
488 	int eccbytes = chip->ecc.bytes;
489 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
490 	int eccsteps = chip->ecc.steps;
492 	uint8_t *oob = chip->oob_poi;
498 	for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
501 		host->col_addr = n * eccsize;
503 		chip->read_buf(mtd, p, eccsize);
505 		host->col_addr = mtd->writesize + n * eccpitch;
507 		if (chip->ecc.prepad) {
508 			chip->read_buf(mtd, oob, chip->ecc.prepad);
509 			oob += chip->ecc.prepad;
512 		stat = chip->ecc.correct(mtd, p, oob, NULL);
515 			mtd->ecc_stats.failed++;
517 			mtd->ecc_stats.corrected += stat;
520 		if (chip->ecc.postpad) {
521 			chip->read_buf(mtd, oob, chip->ecc.postpad);
522 			oob += chip->ecc.postpad;
527 	n = mtd->oobsize - (oob - chip->oob_poi);
529 		chip->read_buf(mtd, oob, n);
532 	_mxc_nand_enable_hwecc(mtd, 0);
533 	chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
534 	eccsteps = chip->ecc.steps;
535 	oob = chip->oob_poi + chip->ecc.prepad;
536 	for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
537 		host->col_addr = mtd->writesize +
539 				 chip->ecc.prepad;
540 		chip->read_buf(mtd, oob, eccbytes);
541 		oob += eccbytes + chip->ecc.postpad;
543 	_mxc_nand_enable_hwecc(mtd, 1);
547 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,  argument
551 	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
552 	int length = mtd->oobsize;
553 	int i, len, status, steps = chip->ecc.steps;
554 	const uint8_t *bufpoi = chip->oob_poi;
556 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
560 		chip->write_buf(mtd, bufpoi, len);
562 		length -= len;
563 		host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
566 		chip->write_buf(mtd, bufpoi, length);
568 	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
569 	status = chip->waitfunc(mtd, chip);
570 	return status & NAND_STATUS_FAIL ? -EIO : 0;
573 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,  argument
579 	int eccsize = chip->ecc.size;
580 	int eccbytes = chip->ecc.bytes;
581 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
582 	uint8_t *oob = chip->oob_poi;
586 	for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
587 		host->col_addr = n * eccsize;
588 		chip->write_buf(mtd, buf, eccsize);
591 		host->col_addr = mtd->writesize + n * eccpitch;
593 		if (chip->ecc.prepad) {
594 			chip->write_buf(mtd, oob, chip->ecc.prepad);
595 			oob += chip->ecc.prepad;
598 		host->col_addr += eccbytes;
601 		if (chip->ecc.postpad) {
602 			chip->write_buf(mtd, oob, chip->ecc.postpad);
603 			oob += chip->ecc.postpad;
607 	size = mtd->oobsize - (oob - chip->oob_poi);
609 		chip->write_buf(mtd, oob, size);
613 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,  argument
619 	int i, n, eccsize = chip->ecc.size;
620 	int eccbytes = chip->ecc.bytes;
621 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
622 	int eccsteps = chip->ecc.steps;
624 	uint8_t *oob = chip->oob_poi;
626 	chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
630 	     n++, eccsteps--, i += eccbytes, p += eccsize) {
631 		host->col_addr = n * eccsize;
633 		chip->write_buf(mtd, p, eccsize);
635 		host->col_addr = mtd->writesize + n * eccpitch;
637 		if (chip->ecc.prepad) {
638 			chip->write_buf(mtd, oob, chip->ecc.prepad);
639 			oob += chip->ecc.prepad;
642 		chip->write_buf(mtd, oob, eccbytes);
645 		if (chip->ecc.postpad) {
646 			chip->write_buf(mtd, oob, chip->ecc.postpad);
647 			oob += chip->ecc.postpad;
652 	i = mtd->oobsize - (oob - chip->oob_poi);
654 		chip->write_buf(mtd, oob, i);
658 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,  argument
661 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
663 	uint32_t ecc_status = readl(&host->regs->ecc_status_result);
664 	int subpages = mtd->writesize / nand_chip->subpagesize;
665 	int pg2blk_shift = nand_chip->phys_erase_shift -
666 			   nand_chip->page_shift;
670 			static int last_bad = -1;
672 			if (last_bad != host->page_addr >> pg2blk_shift) {
673 				last_bad = host->page_addr >> pg2blk_shift;
677 				       last_bad, host->page_addr,
678 				       mtd->writesize / nand_chip->subpagesize
679 					    - subpages);
681 			return -EBADMSG;
684 		subpages--;
697 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,  argument
700 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
704 	 * 1-Bit errors are automatically corrected in HW.  No need for
705 	 * additional correction.  2-Bit errors cannot be corrected by
708 	uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
711 		pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
712 		return -EBADMSG;
719 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,  argument
726 static u_char mxc_nand_read_byte(struct mtd_info *mtd)  argument
728 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
733 		(uint16_t __iomem *)host->regs->main_area[0];
735 		(uint16_t __iomem *)host->regs->spare_area[0];
742 	if (host->status_request)
745 	/* Get column for 16-bit access */
746 	col = host->col_addr >> 1;
749 	if (host->spare_only)
754 	/* Pick upper/lower byte of word from RAM buffer */
755 	ret = nfc_word.bytes[host->col_addr & 0x1];
758 	if (nand_chip->options & NAND_BUSWIDTH_16)
759 		host->col_addr += 2;
761 		host->col_addr++;
766 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)  argument
768 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
773 	pr_debug("mxc_nand_read_word(col = %d)\n", host->col_addr);
775 	col = host->col_addr;
777 	if (col < mtd->writesize && host->spare_only)
778 		col += mtd->writesize;
780 	if (col < mtd->writesize) {
781 		p = (uint16_t __iomem *)(host->regs->main_area[0] +
784 		p = (uint16_t __iomem *)(host->regs->spare_area[0] +
785 				((col - mtd->writesize) >> 1));
806 	host->col_addr = col + 2;
816 static void mxc_nand_write_buf(struct mtd_info *mtd,  argument
819 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
823 	pr_debug("mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
826 	col = host->col_addr;
829 	if (col < mtd->writesize && host->spare_only)
830 		col += mtd->writesize;
832 	n = mtd->writesize + mtd->oobsize - col;
840 		if (col < mtd->writesize) {
841 			p = host->regs->main_area[0] + (col & ~3);
843 			p = host->regs->spare_area[0] -
844 						mtd->writesize + (col & ~3);
858 			n--;
863 			int m = mtd->writesize - col;
865 			if (col >= mtd->writesize)
866 				m += mtd->oobsize;
876 			n -= m;
880 	host->col_addr = col;
888 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)  argument
890 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
894 	pr_debug("mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr,
897 	col = host->col_addr;
900 	if (col < mtd->writesize && host->spare_only)
901 		col += mtd->writesize;
903 	n = mtd->writesize + mtd->oobsize - col;
909 		if (col < mtd->writesize) {
910 			p = host->regs->main_area[0] + (col & ~3);
912 			p = host->regs->spare_area[0] -
913 					mtd->writesize + (col & ~3);
924 			n--;
927 			int m = mtd->writesize - col;
929 			if (col >= mtd->writesize)
930 				m += mtd->oobsize;
937 			n -= m;
941 	host->col_addr = col;
948 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)  argument
950 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
954 	case -1:
956 		if (host->clk_act)
957 			host->clk_act = 0;
961 		if (!host->clk_act)
962 			host->clk_act = 1;
974 void mxc_nand_command(struct mtd_info *mtd, unsigned command,  argument
977 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
984 	host->status_request = false;
986 	/* Command pre-processing step */
990 		host->col_addr = 0;
991 		host->status_request = true;
995 		host->page_addr = page_addr;
996 		host->col_addr = column;
997 		host->spare_only = false;
1001 		host->col_addr = column;
1002 		host->spare_only = true;
1003 		if (host->pagesize_2k)
1008 		if (column >= mtd->writesize) {
1016 			if (host->pagesize_2k) {
1018 				mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1022 			host->col_addr = column - mtd->writesize;
1023 			host->spare_only = true;
1026 			if (!host->pagesize_2k)
1029 			host->spare_only = false;
1030 			host->col_addr = column;
1033 			if (!host->pagesize_2k)
1039 		send_prog_page(host, 0, host->spare_only);
1041 		if (host->pagesize_2k && is_mxc_nfc_1()) {
1043 			send_prog_page(host, 1, host->spare_only);
1044 			send_prog_page(host, 2, host->spare_only);
1045 			send_prog_page(host, 3, host->spare_only);
1055 	if (column != -1) {
1058 		 * spare-only read/write. When the upper layers perform
1063 		if (host->pagesize_2k)
1069 	if (page_addr != -1) {
1070 		u32 page_mask = nand_chip->pagemask;
1078 	/* Command post-processing step */
1086 		if (host->pagesize_2k) {
1090 			send_read_page(host, 0, host->spare_only);
1092 				send_read_page(host, 1, host->spare_only);
1093 				send_read_page(host, 2, host->spare_only);
1094 				send_read_page(host, 3, host->spare_only);
1097 			send_read_page(host, 0, host->spare_only);
1102 		host->col_addr = 0;
1146 	struct mtd_info *mtd;  local
1152 	this->bbt_options |= NAND_BBT_USE_FLASH;
1153 	this->bbt_td = &bbt_main_descr;
1154 	this->bbt_md = &bbt_mirror_descr;
1158 	mtd = &this->mtd;
1159 	host->nand = this;
1162 	this->chip_delay = 5;
1165 	this->dev_ready = mxc_nand_dev_ready;
1166 	this->cmdfunc = mxc_nand_command;
1167 	this->select_chip = mxc_nand_select_chip;
1168 	this->read_byte = mxc_nand_read_byte;
1169 	this->read_word = mxc_nand_read_word;
1170 	this->write_buf = mxc_nand_write_buf;
1171 	this->read_buf = mxc_nand_read_buf;
1173 	host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1175 	host->ip_regs =
1178 	host->clk_act = 1;
1181 	this->ecc.calculate = mxc_nand_calculate_ecc;
1182 	this->ecc.hwctl = mxc_nand_enable_hwecc;
1183 	this->ecc.correct = mxc_nand_correct_data;
1185 		this->ecc.mode = NAND_ECC_HW_SYNDROME;
1186 		this->ecc.read_page = mxc_nand_read_page_syndrome;
1187 		this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1188 		this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1189 		this->ecc.write_page = mxc_nand_write_page_syndrome;
1190 		this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1191 		this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1192 		this->ecc.bytes = 9;
1193 		this->ecc.prepad = 7;
1195 		this->ecc.mode = NAND_ECC_HW;
1199 		this->ecc.strength = 1;
1201 		this->ecc.strength = 4;
1203 	host->pagesize_2k = 0;
1205 	this->ecc.size = 512;
1206 	_mxc_nand_enable_hwecc(mtd, 1);
1208 	this->ecc.layout = &nand_soft_eccoob;
1209 	this->ecc.mode = NAND_ECC_SOFT;
1210 	_mxc_nand_enable_hwecc(mtd, 0);
1213 	this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1217 		this->options |= NAND_BUSWIDTH_16;
1220 	host->pagesize_2k = 1;
1221 	this->ecc.layout = &nand_hw_eccoob2k;
1223 	host->pagesize_2k = 0;
1224 	this->ecc.layout = &nand_hw_eccoob;
1229 	tmp = readnfc(&host->regs->config1);
1232 	writenfc(tmp, &host->regs->config1);
1233 	if (host->pagesize_2k)
1234 		writenfc(64/2, &host->regs->spare_area_size);
1236 		writenfc(16/2, &host->regs->spare_area_size);
1241 	 * Unlock the internal RAM Buffer
1243 	writenfc(0x2, &host->regs->config);
1246 	writenfc(0x0, &host->regs->unlockstart_blkaddr);
1258 	writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1261 	writenfc(0x4, &host->regs->wrprot);
1263 	writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1264 	writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1266 	/* Unlock the internal RAM Buffer */
1268 			&host->ip_regs->wrprot);
1273 				&host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1275 	writenfc(0, &host->ip_regs->ipc);
1277 	tmp = readnfc(&host->ip_regs->config2);
1282 	if (host->pagesize_2k) {
1290 	writenfc(tmp, &host->ip_regs->config2);
1298 	if (!(this->options & NAND_BUSWIDTH_16))
1301 	writenfc(tmp, &host->ip_regs->config3);
1303 	writenfc(0, &host->ip_regs->delay_line);