Lines Matching +full:tcs +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
11 #include <linux/dma-direction.h>
48 #define DENALI_NAND_NAME "denali-nand"
56 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
67 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
69 #define DENALI_INVALID_BANK -1
78 * Direct Addressing - the slave address forms the control information (command
84 return ioread32(denali->host + addr); in denali_direct_read()
90 iowrite32(data, denali->host + addr); in denali_direct_write()
94 * Indexed Addressing - address translation module intervenes in passing the
101 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); in denali_indexed_read()
102 return ioread32(denali->host + DENALI_INDEXED_DATA); in denali_indexed_read()
108 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); in denali_indexed_write()
109 iowrite32(data, denali->host + DENALI_INDEXED_DATA); in denali_indexed_write()
118 uint32_t features = ioread32(denali->reg + FEATURES); in denali_detect_max_banks()
120 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features); in denali_detect_max_banks()
123 if (denali->revision < 0x0501) in denali_detect_max_banks()
124 denali->max_banks <<= 1; in denali_detect_max_banks()
132 iowrite32(U32_MAX, denali->reg + INTR_EN(i)); in denali_enable_irq()
133 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); in denali_enable_irq()
141 iowrite32(0, denali->reg + INTR_EN(i)); in denali_disable_irq()
142 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); in denali_disable_irq()
149 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
166 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in __denali_check_irq()
169 if (i != denali->active_bank) in __denali_check_irq()
172 denali->irq_status |= irq_status; in __denali_check_irq()
178 denali->irq_status = 0; in denali_reset_irq()
179 denali->irq_mask = 0; in denali_reset_irq()
190 if (irq_mask & denali->irq_status) in denali_wait_for_irq()
191 return denali->irq_status; in denali_wait_for_irq()
193 time_left--; in denali_wait_for_irq()
197 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", in denali_wait_for_irq()
202 return denali->irq_status; in denali_wait_for_irq()
209 return denali->irq_status; in denali_check_irq()
219 buf[i] = denali->host_read(denali, addr); in denali_read_buf()
229 denali->host_write(denali, addr, buf[i]); in denali_write_buf()
240 buf16[i] = denali->host_read(denali, addr); in denali_read_buf16()
252 denali->host_write(denali, addr, buf16[i]); in denali_write_buf16()
291 * Some commands are followed by chip->dev_ready or chip->waitfunc. in denali_cmd_ctrl()
297 denali->host_write(denali, DENALI_BANK(denali) | type, dat); in denali_cmd_ctrl()
312 uint8_t *ecc_code = chip->buffers->ecccode; in denali_check_erased_page()
313 int ecc_steps = chip->ecc.steps; in denali_check_erased_page()
314 int ecc_size = chip->ecc.size; in denali_check_erased_page()
315 int ecc_bytes = chip->ecc.bytes; in denali_check_erased_page()
318 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, in denali_check_erased_page()
319 chip->ecc.total); in denali_check_erased_page()
330 chip->ecc.strength); in denali_check_erased_page()
332 mtd->ecc_stats.failed++; in denali_check_erased_page()
334 mtd->ecc_stats.corrected += stat; in denali_check_erased_page()
350 int bank = denali->active_bank; in denali_hw_ecc_fixup()
354 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); in denali_hw_ecc_fixup()
361 * "which sector(s)". We need erase-page check for all sectors. in denali_hw_ecc_fixup()
363 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); in denali_hw_ecc_fixup()
370 * The register holds the maximum of per-sector corrected bitflips. in denali_hw_ecc_fixup()
371 * This is suitable for the return value of the ->read_page() callback. in denali_hw_ecc_fixup()
375 mtd->ecc_stats.corrected += max_bitflips; in denali_hw_ecc_fixup()
384 unsigned int ecc_size = denali->nand.ecc.size; in denali_sw_ecc_fixup()
396 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); in denali_sw_ecc_fixup()
400 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); in denali_sw_ecc_fixup()
424 int offset; in denali_sw_ecc_fixup() local
427 offset = (err_sector * ecc_size + err_byte) * in denali_sw_ecc_fixup()
428 denali->devs_per_cs + err_device; in denali_sw_ecc_fixup()
431 flips_in_byte = hweight8(buf[offset] ^ err_cor_value); in denali_sw_ecc_fixup()
432 buf[offset] ^= err_cor_value; in denali_sw_ecc_fixup()
433 mtd->ecc_stats.corrected += flips_in_byte; in denali_sw_ecc_fixup()
448 return -EIO; in denali_sw_ecc_fixup()
467 denali->host_write(denali, mode, in denali_setup_dma64()
471 denali->host_write(denali, mode, lower_32_bits(dma_addr)); in denali_setup_dma64()
474 denali->host_write(denali, mode, upper_32_bits(dma_addr)); in denali_setup_dma64()
488 denali->host_write(denali, mode | page, in denali_setup_dma32()
492 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); in denali_setup_dma32()
495 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); in denali_setup_dma32()
498 denali->host_write(denali, mode | 0x14000, 0x2400); in denali_setup_dma32()
509 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) in denali_pio_read()
517 *buf32++ = denali->host_read(denali, addr); in denali_pio_read()
521 return -EIO; in denali_pio_read()
526 return irq_status & ecc_err_mask ? -EBADMSG : 0; in denali_pio_read()
540 denali->host_write(denali, addr, *buf32++); in denali_pio_write()
545 return -EIO; in denali_pio_write()
567 dma_addr = dma_map_single(denali->dev, buf, size, dir); in denali_dma_xfer()
568 if (dma_mapping_error(denali->dev, dma_addr)) { in denali_dma_xfer()
569 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); in denali_dma_xfer()
581 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { in denali_dma_xfer()
589 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); in denali_dma_xfer()
591 * The ->setup_dma() hook kicks DMA by using the data/command in denali_dma_xfer()
595 ioread32(denali->reg + DMA_ENABLE); in denali_dma_xfer()
598 denali->setup_dma(denali, dma_addr, page, write); in denali_dma_xfer()
602 ret = -EIO; in denali_dma_xfer()
604 ret = -EBADMSG; in denali_dma_xfer()
606 iowrite32(0, denali->reg + DMA_ENABLE); in denali_dma_xfer()
608 dma_unmap_single(denali->dev, dma_addr, size, dir); in denali_dma_xfer()
619 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); in denali_data_xfer()
621 denali->reg + TRANSFER_SPARE_REG); in denali_data_xfer()
623 if (denali->dma_avail) in denali_data_xfer()
635 int writesize = mtd->writesize; in denali_oob_xfer()
636 int oobsize = mtd->oobsize; in denali_oob_xfer()
637 uint8_t *bufpoi = chip->oob_poi; in denali_oob_xfer()
638 int ecc_steps = chip->ecc.steps; in denali_oob_xfer()
639 int ecc_size = chip->ecc.size; in denali_oob_xfer()
640 int ecc_bytes = chip->ecc.bytes; in denali_oob_xfer()
641 int oob_skip = denali->oob_skip_bytes; in denali_oob_xfer()
646 chip->cmdfunc(mtd, start_cmd, writesize, page); in denali_oob_xfer()
648 chip->write_buf(mtd, bufpoi, oob_skip); in denali_oob_xfer()
650 chip->read_buf(mtd, bufpoi, oob_skip); in denali_oob_xfer()
661 len = writesize - pos; in denali_oob_xfer()
663 chip->cmdfunc(mtd, rnd_cmd, pos, -1); in denali_oob_xfer()
665 chip->write_buf(mtd, bufpoi, len); in denali_oob_xfer()
667 chip->read_buf(mtd, bufpoi, len); in denali_oob_xfer()
670 len = ecc_bytes - len; in denali_oob_xfer()
671 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1); in denali_oob_xfer()
673 chip->write_buf(mtd, bufpoi, len); in denali_oob_xfer()
675 chip->read_buf(mtd, bufpoi, len); in denali_oob_xfer()
681 len = oobsize - (bufpoi - chip->oob_poi); in denali_oob_xfer()
682 chip->cmdfunc(mtd, rnd_cmd, size - len, -1); in denali_oob_xfer()
684 chip->write_buf(mtd, bufpoi, len); in denali_oob_xfer()
686 chip->read_buf(mtd, bufpoi, len); in denali_oob_xfer()
693 int writesize = mtd->writesize; in denali_read_page_raw()
694 int oobsize = mtd->oobsize; in denali_read_page_raw()
695 int ecc_steps = chip->ecc.steps; in denali_read_page_raw()
696 int ecc_size = chip->ecc.size; in denali_read_page_raw()
697 int ecc_bytes = chip->ecc.bytes; in denali_read_page_raw()
698 void *tmp_buf = denali->buf; in denali_read_page_raw()
699 int oob_skip = denali->oob_skip_bytes; in denali_read_page_raw()
716 len = writesize - pos; in denali_read_page_raw()
721 len = ecc_size - len; in denali_read_page_raw()
730 uint8_t *oob = chip->oob_poi; in denali_read_page_raw()
744 len = writesize - pos; in denali_read_page_raw()
749 len = ecc_bytes - len; in denali_read_page_raw()
757 len = oobsize - (oob - chip->oob_poi); in denali_read_page_raw()
758 memcpy(oob, tmp_buf + size - len, len); in denali_read_page_raw()
782 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); in denali_write_oob()
783 status = chip->waitfunc(mtd, chip); in denali_write_oob()
785 return status & NAND_STATUS_FAIL ? -EIO : 0; in denali_write_oob()
796 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0); in denali_read_page()
797 if (ret && ret != -EBADMSG) in denali_read_page()
800 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) in denali_read_page()
802 else if (ret == -EBADMSG) in denali_read_page()
824 int writesize = mtd->writesize; in denali_write_page_raw()
825 int oobsize = mtd->oobsize; in denali_write_page_raw()
826 int ecc_steps = chip->ecc.steps; in denali_write_page_raw()
827 int ecc_size = chip->ecc.size; in denali_write_page_raw()
828 int ecc_bytes = chip->ecc.bytes; in denali_write_page_raw()
829 void *tmp_buf = denali->buf; in denali_write_page_raw()
830 int oob_skip = denali->oob_skip_bytes; in denali_write_page_raw()
850 len = writesize - pos; in denali_write_page_raw()
855 len = ecc_size - len; in denali_write_page_raw()
864 const uint8_t *oob = chip->oob_poi; in denali_write_page_raw()
878 len = writesize - pos; in denali_write_page_raw()
883 len = ecc_bytes - len; in denali_write_page_raw()
891 len = oobsize - (oob - chip->oob_poi); in denali_write_page_raw()
892 memcpy(tmp_buf + size - len, oob, len); in denali_write_page_raw()
903 return denali_data_xfer(denali, (void *)buf, mtd->writesize, in denali_write_page()
911 denali->active_bank = chip; in denali_select_chip()
932 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, in denali_erase()
958 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); in denali_setup_data_interface()
960 return -EINVAL; in denali_setup_data_interface()
967 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); in denali_setup_data_interface()
969 return -EINVAL; in denali_setup_data_interface()
974 /* tREA -> ACC_CLKS */ in denali_setup_data_interface()
975 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); in denali_setup_data_interface()
978 tmp = ioread32(denali->reg + ACC_CLKS); in denali_setup_data_interface()
981 iowrite32(tmp, denali->reg + ACC_CLKS); in denali_setup_data_interface()
983 /* tRWH -> RE_2_WE */ in denali_setup_data_interface()
984 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); in denali_setup_data_interface()
987 tmp = ioread32(denali->reg + RE_2_WE); in denali_setup_data_interface()
990 iowrite32(tmp, denali->reg + RE_2_WE); in denali_setup_data_interface()
992 /* tRHZ -> RE_2_RE */ in denali_setup_data_interface()
993 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); in denali_setup_data_interface()
996 tmp = ioread32(denali->reg + RE_2_RE); in denali_setup_data_interface()
999 iowrite32(tmp, denali->reg + RE_2_RE); in denali_setup_data_interface()
1002 * tCCS, tWHR -> WE_2_RE in denali_setup_data_interface()
1007 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_data_interface()
1010 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); in denali_setup_data_interface()
1013 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); in denali_setup_data_interface()
1015 /* tADL -> ADDR_2_DATA */ in denali_setup_data_interface()
1019 if (denali->revision < 0x0501) in denali_setup_data_interface()
1022 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); in denali_setup_data_interface()
1025 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); in denali_setup_data_interface()
1028 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); in denali_setup_data_interface()
1030 /* tREH, tWH -> RDWR_EN_HI_CNT */ in denali_setup_data_interface()
1031 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), in denali_setup_data_interface()
1035 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); in denali_setup_data_interface()
1038 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); in denali_setup_data_interface()
1040 /* tRP, tWP -> RDWR_EN_LO_CNT */ in denali_setup_data_interface()
1041 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); in denali_setup_data_interface()
1042 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), in denali_setup_data_interface()
1045 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); in denali_setup_data_interface()
1048 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); in denali_setup_data_interface()
1051 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); in denali_setup_data_interface()
1053 /* tCS, tCEA -> CS_SETUP_CNT */ in denali_setup_data_interface()
1054 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, in denali_setup_data_interface()
1055 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, in denali_setup_data_interface()
1059 tmp = ioread32(denali->reg + CS_SETUP_CNT); in denali_setup_data_interface()
1062 iowrite32(tmp, denali->reg + CS_SETUP_CNT); in denali_setup_data_interface()
1072 for (i = 0; i < denali->max_banks; i++) { in denali_reset_banks()
1073 denali->active_bank = i; in denali_reset_banks()
1078 denali->reg + DEVICE_RESET); in denali_reset_banks()
1086 dev_dbg(denali->dev, "%d chips connected\n", i); in denali_reset_banks()
1087 denali->max_banks = i; in denali_reset_banks()
1096 if (!denali->revision) in denali_hw_init()
1097 denali->revision = swab16(ioread32(denali->reg + REVISION)); in denali_hw_init()
1103 denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES; in denali_hw_init()
1104 iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES); in denali_hw_init()
1106 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); in denali_hw_init()
1107 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); in denali_hw_init()
1109 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); in denali_hw_init()
1122 int oobavail = mtd->oobsize - denali->oob_skip_bytes; in denali_ecc_setup()
1129 if (chip->ecc.size && chip->ecc.strength) in denali_ecc_setup()
1130 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail); in denali_ecc_setup()
1136 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) { in denali_ecc_setup()
1137 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail); in denali_ecc_setup()
1143 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail); in denali_ecc_setup()
1155 return -ERANGE; in denali_ooblayout_ecc()
1157 oobregion->offset = denali->oob_skip_bytes; in denali_ooblayout_ecc()
1158 oobregion->length = chip->ecc.total; in denali_ooblayout_ecc()
1170 return -ERANGE; in denali_ooblayout_free()
1172 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; in denali_ooblayout_free()
1173 oobregion->length = mtd->oobsize - oobregion->offset; in denali_ooblayout_free()
1185 struct nand_chip *chip = &denali->nand; in denali_multidev_fixup()
1195 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); in denali_multidev_fixup()
1198 * On some SoCs, DEVICES_CONNECTED is not auto-detected. in denali_multidev_fixup()
1201 if (denali->devs_per_cs == 0) { in denali_multidev_fixup()
1202 denali->devs_per_cs = 1; in denali_multidev_fixup()
1203 iowrite32(1, denali->reg + DEVICES_CONNECTED); in denali_multidev_fixup()
1206 if (denali->devs_per_cs == 1) in denali_multidev_fixup()
1209 if (denali->devs_per_cs != 2) { in denali_multidev_fixup()
1210 dev_err(denali->dev, "unsupported number of devices %d\n", in denali_multidev_fixup()
1211 denali->devs_per_cs); in denali_multidev_fixup()
1212 return -EINVAL; in denali_multidev_fixup()
1216 mtd->size <<= 1; in denali_multidev_fixup()
1217 mtd->erasesize <<= 1; in denali_multidev_fixup()
1218 mtd->writesize <<= 1; in denali_multidev_fixup()
1219 mtd->oobsize <<= 1; in denali_multidev_fixup()
1220 chip->chipsize <<= 1; in denali_multidev_fixup()
1221 chip->page_shift += 1; in denali_multidev_fixup()
1222 chip->phys_erase_shift += 1; in denali_multidev_fixup()
1223 chip->bbt_erase_shift += 1; in denali_multidev_fixup()
1224 chip->chip_shift += 1; in denali_multidev_fixup()
1225 chip->pagemask <<= 1; in denali_multidev_fixup()
1226 chip->ecc.size <<= 1; in denali_multidev_fixup()
1227 chip->ecc.bytes <<= 1; in denali_multidev_fixup()
1228 chip->ecc.strength <<= 1; in denali_multidev_fixup()
1229 denali->oob_skip_bytes <<= 1; in denali_multidev_fixup()
1236 struct nand_chip *chip = &denali->nand; in denali_init()
1238 u32 features = ioread32(denali->reg + FEATURES); in denali_init()
1247 denali->active_bank = DENALI_INVALID_BANK; in denali_init()
1249 chip->flash_node = dev_of_offset(denali->dev); in denali_init()
1251 if (!mtd->name) in denali_init()
1252 mtd->name = "denali-nand"; in denali_init()
1254 chip->select_chip = denali_select_chip; in denali_init()
1255 chip->read_byte = denali_read_byte; in denali_init()
1256 chip->write_byte = denali_write_byte; in denali_init()
1257 chip->read_word = denali_read_word; in denali_init()
1258 chip->cmd_ctrl = denali_cmd_ctrl; in denali_init()
1259 chip->dev_ready = denali_dev_ready; in denali_init()
1260 chip->waitfunc = denali_waitfunc; in denali_init()
1263 denali->host_read = denali_indexed_read; in denali_init()
1264 denali->host_write = denali_indexed_write; in denali_init()
1266 denali->host_read = denali_direct_read; in denali_init()
1267 denali->host_write = denali_direct_write; in denali_init()
1271 if (denali->clk_x_rate) in denali_init()
1272 chip->setup_data_interface = denali_setup_data_interface; in denali_init()
1274 ret = nand_scan_ident(mtd, denali->max_banks, NULL); in denali_init()
1278 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA) in denali_init()
1279 denali->dma_avail = 1; in denali_init()
1281 if (denali->dma_avail) { in denali_init()
1282 chip->buf_align = ARCH_DMA_MINALIGN; in denali_init()
1283 if (denali->caps & DENALI_CAP_DMA_64BIT) in denali_init()
1284 denali->setup_dma = denali_setup_dma64; in denali_init()
1286 denali->setup_dma = denali_setup_dma32; in denali_init()
1288 chip->buf_align = 4; in denali_init()
1291 chip->options |= NAND_USE_BOUNCE_BUFFER; in denali_init()
1292 chip->bbt_options |= NAND_BBT_USE_FLASH; in denali_init()
1293 chip->bbt_options |= NAND_BBT_NO_OOB; in denali_init()
1294 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; in denali_init()
1297 chip->options |= NAND_NO_SUBPAGE_WRITE; in denali_init()
1301 dev_err(denali->dev, "Failed to setup ECC settings.\n"); in denali_init()
1305 dev_dbg(denali->dev, in denali_init()
1307 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); in denali_init()
1310 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), in denali_init()
1311 denali->reg + ECC_CORRECTION); in denali_init()
1312 iowrite32(mtd->erasesize / mtd->writesize, in denali_init()
1313 denali->reg + PAGES_PER_BLOCK); in denali_init()
1314 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, in denali_init()
1315 denali->reg + DEVICE_WIDTH); in denali_init()
1316 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG, in denali_init()
1317 denali->reg + TWO_ROW_ADDR_CYCLES); in denali_init()
1318 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); in denali_init()
1319 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); in denali_init()
1321 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); in denali_init()
1322 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); in denali_init()
1323 /* chip->ecc.steps is set by nand_scan_tail(); not available here */ in denali_init()
1324 iowrite32(mtd->writesize / chip->ecc.size, in denali_init()
1325 denali->reg + CFG_NUM_DATA_BLOCKS); in denali_init()
1329 nand_oob.eccbytes = denali->nand.ecc.bytes; in denali_init()
1330 denali->nand.ecc.layout = &nand_oob; in denali_init()
1332 if (chip->options & NAND_BUSWIDTH_16) { in denali_init()
1333 chip->read_buf = denali_read_buf16; in denali_init()
1334 chip->write_buf = denali_write_buf16; in denali_init()
1336 chip->read_buf = denali_read_buf; in denali_init()
1337 chip->write_buf = denali_write_buf; in denali_init()
1339 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS; in denali_init()
1340 chip->ecc.read_page = denali_read_page; in denali_init()
1341 chip->ecc.read_page_raw = denali_read_page_raw; in denali_init()
1342 chip->ecc.write_page = denali_write_page; in denali_init()
1343 chip->ecc.write_page_raw = denali_write_page_raw; in denali_init()
1344 chip->ecc.read_oob = denali_read_oob; in denali_init()
1345 chip->ecc.write_oob = denali_write_oob; in denali_init()
1346 chip->erase = denali_erase; in denali_init()
1353 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not in denali_init()
1355 * guarantee DMA-safe alignment. in denali_init()
1357 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); in denali_init()
1358 if (!denali->buf) in denali_init()
1359 return -ENOMEM; in denali_init()
1367 dev_err(denali->dev, "Failed to register MTD: %d\n", ret); in denali_init()
1373 kfree(denali->buf); in denali_init()