5  * Xilinx Zynq SD Host Controller Interface
27 	struct sdhci_host *host;  member
58 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)  in arasan_zynqmp_dll_reset()  argument
63 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);  in arasan_zynqmp_dll_reset()
65 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);  in arasan_zynqmp_dll_reset()
72 	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))  in arasan_zynqmp_dll_reset()
75 			dev_err(mmc_dev(host->mmc),  in arasan_zynqmp_dll_reset()
84 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);  in arasan_zynqmp_dll_reset()
92 	struct sdhci_host *host;  in arasan_sdhci_execute_tuning()  local
99 	host = priv->host;  in arasan_sdhci_execute_tuning()
102 	ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);  in arasan_sdhci_execute_tuning()
104 	sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);  in arasan_sdhci_execute_tuning()
108 	arasan_zynqmp_dll_reset(host, deviceid);  in arasan_sdhci_execute_tuning()
110 	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);  in arasan_sdhci_execute_tuning()
111 	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);  in arasan_sdhci_execute_tuning()
129 		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,  in arasan_sdhci_execute_tuning()
132 		sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);  in arasan_sdhci_execute_tuning()
133 		sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);  in arasan_sdhci_execute_tuning()
136 		ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);  in arasan_sdhci_execute_tuning()
145 		sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);  in arasan_sdhci_execute_tuning()
154 	arasan_zynqmp_dll_reset(host, deviceid);  in arasan_sdhci_execute_tuning()
157 	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,  in arasan_sdhci_execute_tuning()
160 	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);  in arasan_sdhci_execute_tuning()
165 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)  in arasan_sdhci_set_tapdelay()  argument
167 	struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);  in arasan_sdhci_set_tapdelay()
168 	struct mmc *mmc = (struct mmc *)host->mmc;  in arasan_sdhci_set_tapdelay()
178 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)  in arasan_sdhci_set_control_reg()  argument
180 	struct mmc *mmc = (struct mmc *)host->mmc;  in arasan_sdhci_set_control_reg()
187 		reg = sdhci_readw(host, SDHCI_HOST_CTRL2);  in arasan_sdhci_set_control_reg()
189 		sdhci_writew(host, reg, SDHCI_HOST_CTRL2);  in arasan_sdhci_set_control_reg()
194 		reg = sdhci_readw(host, SDHCI_HOST_CTRL2);  in arasan_sdhci_set_control_reg()
215 		sdhci_writew(host, reg, SDHCI_HOST_CTRL2);  in arasan_sdhci_set_control_reg()
233 	struct sdhci_host *host;  in arasan_sdhci_probe()  local
238 	host = priv->host;  in arasan_sdhci_probe()
260 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |  in arasan_sdhci_probe()
264 	host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;  in arasan_sdhci_probe()
268 		host->quirks |= SDHCI_QUIRK_NO_1_8_V;  in arasan_sdhci_probe()
270 	host->max_clk = clock;  in arasan_sdhci_probe()
272 	ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,  in arasan_sdhci_probe()
274 	host->mmc = &plat->mmc;  in arasan_sdhci_probe()
277 	host->mmc->priv = host;  in arasan_sdhci_probe()
278 	host->mmc->dev = dev;  in arasan_sdhci_probe()
279 	upriv->mmc = host->mmc;  in arasan_sdhci_probe()
289 	priv->host = calloc(1, sizeof(struct sdhci_host));  in arasan_sdhci_ofdata_to_platdata()
290 	if (!priv->host)  in arasan_sdhci_ofdata_to_platdata()
293 	priv->host->name = dev->name;  in arasan_sdhci_ofdata_to_platdata()
296 	priv->host->ops = &arasan_ops;  in arasan_sdhci_ofdata_to_platdata()
299 	priv->host->ioaddr = (void *)dev_read_addr(dev);  in arasan_sdhci_ofdata_to_platdata()
300 	if (IS_ERR(priv->host->ioaddr))  in arasan_sdhci_ofdata_to_platdata()
301 		return PTR_ERR(priv->host->ioaddr);  in arasan_sdhci_ofdata_to_platdata()