136 	u32 var;  in xenon_mmc_phy_init()  local
139 	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
140 	var |= SAMPL_INV_QSP_PHASE_SELECT;  in xenon_mmc_phy_init()
146 		var |= EMMC_PHY_SLOW_MODE;  in xenon_mmc_phy_init()
147 	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
153 		var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_init()
154 		if (var & SDHCI_CLOCK_INT_STABLE)  in xenon_mmc_phy_init()
166 	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
167 	var |= PHY_INITIALIZAION;  in xenon_mmc_phy_init()
168 	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
179 		var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
180 		var &= PHY_INITIALIZAION;  in xenon_mmc_phy_init()
181 		if (!var)  in xenon_mmc_phy_init()
212 	u32 var;  in xenon_mmc_phy_set()  local
215 	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);  in xenon_mmc_phy_set()
216 	var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |  in xenon_mmc_phy_set()
218 	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);  in xenon_mmc_phy_set()
221 	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);  in xenon_mmc_phy_set()
222 	var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);  in xenon_mmc_phy_set()
223 	var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);  in xenon_mmc_phy_set()
224 	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);  in xenon_mmc_phy_set()
237 		var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_set()
238 		var |= OUTPUT_QSN_PHASE_SELECT;  in xenon_mmc_phy_set()
239 		sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_set()
246 	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
247 	var &= ~SDHCI_CLOCK_CARD_EN;  in xenon_mmc_phy_set()
248 	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
250 	var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);  in xenon_mmc_phy_set()
252 		var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;  in xenon_mmc_phy_set()
254 		var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |  in xenon_mmc_phy_set()
257 	sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);  in xenon_mmc_phy_set()
260 	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
261 	var |= SDHCI_CLOCK_CARD_EN;  in xenon_mmc_phy_set()
262 	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
270 	u32 var;  in xenon_mmc_set_acg()  local
272 	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);  in xenon_mmc_set_acg()
274 		var &= ~AUTO_CLKGATE_DISABLE_MASK;  in xenon_mmc_set_acg()
276 		var |= AUTO_CLKGATE_DISABLE_MASK;  in xenon_mmc_set_acg()
278 	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);  in xenon_mmc_set_acg()
286 	u32 var;  in xenon_mmc_enable_slot()  local
288 	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);  in xenon_mmc_enable_slot()
289 	var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;  in xenon_mmc_enable_slot()
290 	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);  in xenon_mmc_enable_slot()
296 	u32 var;  in xenon_mmc_enable_parallel_tran()  local
298 	var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);  in xenon_mmc_enable_parallel_tran()
299 	var |= SLOT_MASK(slot);  in xenon_mmc_enable_parallel_tran()
300 	sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);  in xenon_mmc_enable_parallel_tran()
305 	u32 var;  in xenon_mmc_disable_tuning()  local
308 	var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);  in xenon_mmc_disable_tuning()
309 	var &= ~RETUNING_COMPATIBLE;  in xenon_mmc_disable_tuning()
310 	sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);  in xenon_mmc_disable_tuning()
313 	var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);  in xenon_mmc_disable_tuning()
314 	var &= ~SDHCI_RETUNE_EVT_INTSIG;  in xenon_mmc_disable_tuning()
315 	sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);  in xenon_mmc_disable_tuning()