Lines Matching full:host
26 /* Register Offset of SD Host Controller SOCP self-defined register */
121 struct sdhci_host host; member
131 static int xenon_mmc_phy_init(struct sdhci_host *host) in xenon_mmc_phy_init() argument
133 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_mmc_phy_init()
139 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
147 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
149 /* Poll for host MMC PHY clock init to be stable */ in xenon_mmc_phy_init()
153 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_init()
166 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
168 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
175 /* Poll for host eMMC PHY init to complete */ in xenon_mmc_phy_init()
179 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
184 /* wait for host eMMC PHY init to complete */ in xenon_mmc_phy_init()
199 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host) in armada_3700_soc_pad_voltage_set() argument
201 struct xenon_sdhci_priv *priv = host->mmc->priv; in armada_3700_soc_pad_voltage_set()
209 static void xenon_mmc_phy_set(struct sdhci_host *host) in xenon_mmc_phy_set() argument
211 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_mmc_phy_set()
215 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
218 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
221 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
224 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
237 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
239 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
246 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
248 sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
250 var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
251 if (host->mmc->ddr_mode) { in xenon_mmc_phy_set()
257 sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
260 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
262 sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
264 xenon_mmc_phy_init(host); in xenon_mmc_phy_set()
268 static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable) in xenon_mmc_set_acg() argument
272 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
278 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
284 static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot) in xenon_mmc_enable_slot() argument
288 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
290 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
294 static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot) in xenon_mmc_enable_parallel_tran() argument
298 var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
300 sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
303 static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot) in xenon_mmc_disable_tuning() argument
308 var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL); in xenon_mmc_disable_tuning()
310 sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL); in xenon_mmc_disable_tuning()
313 var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_mmc_disable_tuning()
315 sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE); in xenon_mmc_disable_tuning()
319 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host) in xenon_mask_cmd_conflict_err() argument
323 reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
325 sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
329 static void xenon_sdhci_set_ios_post(struct sdhci_host *host) in xenon_sdhci_set_ios_post() argument
331 struct xenon_sdhci_priv *priv = host->mmc->priv; in xenon_sdhci_set_ios_post()
332 uint speed = host->mmc->tran_speed; in xenon_sdhci_set_ios_post()
335 if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) == in xenon_sdhci_set_ios_post()
340 if (IS_SD(host->mmc)) { in xenon_sdhci_set_ios_post()
343 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()
357 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()
366 xenon_mmc_phy_set(host); in xenon_sdhci_set_ios_post()
379 struct sdhci_host *host = dev_get_priv(dev); in xenon_sdhci_probe() local
382 host->mmc = &plat->mmc; in xenon_sdhci_probe()
383 host->mmc->priv = host; in xenon_sdhci_probe()
384 host->mmc->dev = dev; in xenon_sdhci_probe()
385 upriv->mmc = host->mmc; in xenon_sdhci_probe()
388 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR; in xenon_sdhci_probe()
394 xenon_mmc_set_acg(host, false); in xenon_sdhci_probe()
397 xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION); in xenon_sdhci_probe()
404 armada_3700_soc_pad_voltage_set(host); in xenon_sdhci_probe()
406 host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz; in xenon_sdhci_probe()
410 host->host_caps |= MMC_MODE_8BIT; in xenon_sdhci_probe()
413 host->host_caps |= MMC_MODE_4BIT; in xenon_sdhci_probe()
422 host->ops = &xenon_sdhci_ops; in xenon_sdhci_probe()
424 host->max_clk = XENON_MMC_MAX_CLK; in xenon_sdhci_probe()
425 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); in xenon_sdhci_probe()
434 xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION); in xenon_sdhci_probe()
437 xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION); in xenon_sdhci_probe()
440 xenon_mmc_set_acg(host, true); in xenon_sdhci_probe()
442 xenon_mask_cmd_conflict_err(host); in xenon_sdhci_probe()
449 struct sdhci_host *host = dev_get_priv(dev); in xenon_sdhci_ofdata_to_platdata() local
453 host->name = dev->name; in xenon_sdhci_ofdata_to_platdata()
454 host->ioaddr = (void *)devfdt_get_addr(dev); in xenon_sdhci_ofdata_to_platdata()