Lines Matching full:bit
11 #define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
12 #define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
13 #define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
14 #define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
15 #define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
24 #define TMIO_SD_STOP_SEC BIT(8) /* use sector count */
25 #define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
32 #define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */
33 #define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */
34 #define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */
35 #define TMIO_SD_INFO1_CMP BIT(2) /* data complete */
36 #define TMIO_SD_INFO1_RSP BIT(0) /* response complete */
38 #define TMIO_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
39 #define TMIO_SD_INFO2_CBSY BIT(14) /* command busy */
40 #define TMIO_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
41 #define TMIO_SD_INFO2_BWE BIT(9) /* write buffer ready */
42 #define TMIO_SD_INFO2_BRE BIT(8) /* read buffer ready */
43 #define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
44 #define TMIO_SD_INFO2_ERR_RTO BIT(6) /* response time out */
45 #define TMIO_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
46 #define TMIO_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
47 #define TMIO_SD_INFO2_ERR_TO BIT(3) /* time out error */
48 #define TMIO_SD_INFO2_ERR_END BIT(2) /* END bit error */
49 #define TMIO_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
50 #define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
55 #define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
56 #define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
57 #define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
58 #define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
59 #define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
60 #define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
61 #define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
62 #define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
63 #define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
65 #define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
67 #define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
68 #define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
77 #define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
79 #define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
84 #define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */
91 #define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
92 #define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
94 #define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
96 #define TMIO_SD_DMA_RST_RD BIT(9)
97 #define TMIO_SD_DMA_RST_WR BIT(8)
99 #define TMIO_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
100 #define TMIO_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
101 #define TMIO_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
104 #define TMIO_SD_DMA_INFO2_ERR_RD BIT(17)
105 #define TMIO_SD_DMA_INFO2_ERR_WR BIT(16)
123 #define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
124 #define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
125 #define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
126 #define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
127 #define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */
128 #define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */
129 #define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */
130 #define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */