Lines Matching +full:0 +full:x42c
10 #define TMIO_SD_CMD 0x000 /* command */
13 #define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
16 #define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
22 #define TMIO_SD_ARG 0x008 /* command argument */
23 #define TMIO_SD_STOP 0x010 /* stop action control */
25 #define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
26 #define TMIO_SD_SECCNT 0x014 /* sector counter */
27 #define TMIO_SD_RSP10 0x018 /* response[39:8] */
28 #define TMIO_SD_RSP32 0x020 /* response[71:40] */
29 #define TMIO_SD_RSP54 0x028 /* response[103:72] */
30 #define TMIO_SD_RSP76 0x030 /* response[127:104] */
31 #define TMIO_SD_INFO1 0x038 /* IRQ status 1 */
36 #define TMIO_SD_INFO1_RSP BIT(0) /* response complete */
37 #define TMIO_SD_INFO2 0x03c /* IRQ status 2 */
50 #define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
51 #define TMIO_SD_INFO1_MASK 0x040
52 #define TMIO_SD_INFO2_MASK 0x044
53 #define TMIO_SD_CLKCTL 0x048 /* clock divisor */
54 #define TMIO_SD_CLKCTL_DIV_MASK 0x104ff
63 #define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
64 #define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
66 #define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
69 #define TMIO_SD_SIZE 0x04c /* block size */
70 #define TMIO_SD_OPTION 0x050
73 #define TMIO_SD_OPTION_WIDTH_4 (0 << 13)
75 #define TMIO_SD_BUF 0x060 /* read/write buffer */
76 #define TMIO_SD_EXTMODE 0x1b0
77 #define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
78 #define TMIO_SD_SOFT_RST 0x1c0
79 #define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
80 #define TMIO_SD_VERSION 0x1c4 /* version register */
81 #define TMIO_SD_VERSION_IP 0xff /* IP version */
82 #define TMIO_SD_HOST_MODE 0x1c8
83 #define TMIO_SD_IF_MODE 0x1cc
84 #define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */
85 #define TMIO_SD_VOLT 0x1e4 /* voltage switch */
86 #define TMIO_SD_VOLT_MASK (3 << 0)
87 #define TMIO_SD_VOLT_OFF (0 << 0)
88 #define TMIO_SD_VOLT_330 (1 << 0)/* 3.3V signal */
89 #define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
90 #define TMIO_SD_DMA_MODE 0x410
91 #define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
92 #define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
93 #define TMIO_SD_DMA_CTL 0x414
94 #define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
95 #define TMIO_SD_DMA_RST 0x418
98 #define TMIO_SD_DMA_INFO1 0x420
102 #define TMIO_SD_DMA_INFO1_MASK 0x424
103 #define TMIO_SD_DMA_INFO2 0x428
106 #define TMIO_SD_DMA_INFO2_MASK 0x42c
107 #define TMIO_SD_DMA_ADDR_L 0x440
108 #define TMIO_SD_DMA_ADDR_H 0x444
111 #define TMIO_SD_DMA_MINALIGN 0x10
123 #define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */