Lines Matching +full:sh +full:- +full:mmcif
1 // SPDX-License-Identifier: GPL-2.0
3 * MMCIF driver.
29 state = sh_mmcif_read(&host->regs->ce_int); in sh_mmcif_intr()
30 state &= sh_mmcif_read(&host->regs->ce_int_mask); in sh_mmcif_intr()
33 sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int); in sh_mmcif_intr()
34 sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask); in sh_mmcif_intr()
37 sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int); in sh_mmcif_intr()
38 sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask); in sh_mmcif_intr()
40 if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY) in sh_mmcif_intr()
41 return -EAGAIN; in sh_mmcif_intr()
44 sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int); in sh_mmcif_intr()
45 sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask); in sh_mmcif_intr()
48 sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int); in sh_mmcif_intr()
49 sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask); in sh_mmcif_intr()
53 INT_BUFRE), &host->regs->ce_int); in sh_mmcif_intr()
54 sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask); in sh_mmcif_intr()
57 sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int); in sh_mmcif_intr()
58 sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask); in sh_mmcif_intr()
61 sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int); in sh_mmcif_intr()
62 sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask); in sh_mmcif_intr()
66 &host->regs->ce_int); in sh_mmcif_intr()
67 sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask); in sh_mmcif_intr()
71 sh_mmcif_write(~state, &host->regs->ce_int); in sh_mmcif_intr()
72 sh_mmcif_bitclr(state, &host->regs->ce_int_mask); in sh_mmcif_intr()
75 return -EAGAIN; in sh_mmcif_intr()
78 host->sd_error = 1; in sh_mmcif_intr()
81 host->wait_int = 1; in sh_mmcif_intr()
90 timeout--; in mmcif_wait_interrupt_flag()
107 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
108 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
114 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
116 sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk, in sh_mmcif_clock_control()
117 clk) - 1) - 1) << 16, in sh_mmcif_clock_control()
118 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
126 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
129 sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version); in sh_mmcif_sync_reset()
130 sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version); in sh_mmcif_sync_reset()
132 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
134 sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc); in sh_mmcif_sync_reset()
142 host->sd_error = 0; in sh_mmcif_error_manage()
143 host->wait_int = 0; in sh_mmcif_error_manage()
145 state1 = sh_mmcif_read(&host->regs->ce_host_sts1); in sh_mmcif_error_manage()
146 state2 = sh_mmcif_read(&host->regs->ce_host_sts2); in sh_mmcif_error_manage()
148 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1)); in sh_mmcif_error_manage()
150 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2)); in sh_mmcif_error_manage()
154 sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); in sh_mmcif_error_manage()
155 sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); in sh_mmcif_error_manage()
157 timeout--; in sh_mmcif_error_manage()
161 return -EILSEQ; in sh_mmcif_error_manage()
163 if (!(sh_mmcif_read(&host->regs->ce_host_sts1) in sh_mmcif_error_manage()
168 return -EILSEQ; in sh_mmcif_error_manage()
172 ret = -EILSEQ; in sh_mmcif_error_manage()
174 ret = -ETIMEDOUT; in sh_mmcif_error_manage()
176 ret = -EILSEQ; in sh_mmcif_error_manage()
185 unsigned long *p = (unsigned long *)data->dest; in sh_mmcif_single_read()
189 return -EIO; in sh_mmcif_single_read()
192 host->wait_int = 0; in sh_mmcif_single_read()
195 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); in sh_mmcif_single_read()
197 if (time == 0 || host->sd_error != 0) in sh_mmcif_single_read()
200 host->wait_int = 0; in sh_mmcif_single_read()
202 sh_mmcif_read(&host->regs->ce_block_set)) + 3; in sh_mmcif_single_read()
204 *p++ = sh_mmcif_read(&host->regs->ce_data); in sh_mmcif_single_read()
207 sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask); in sh_mmcif_single_read()
209 if (time == 0 || host->sd_error != 0) in sh_mmcif_single_read()
212 host->wait_int = 0; in sh_mmcif_single_read()
221 unsigned long *p = (unsigned long *)data->dest; in sh_mmcif_multi_read()
225 return -EIO; in sh_mmcif_multi_read()
228 host->wait_int = 0; in sh_mmcif_multi_read()
229 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); in sh_mmcif_multi_read()
230 for (j = 0; j < data->blocks; j++) { in sh_mmcif_multi_read()
231 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); in sh_mmcif_multi_read()
233 if (time == 0 || host->sd_error != 0) in sh_mmcif_multi_read()
236 host->wait_int = 0; in sh_mmcif_multi_read()
238 *p++ = sh_mmcif_read(&host->regs->ce_data); in sh_mmcif_multi_read()
250 const unsigned long *p = (unsigned long *)data->dest; in sh_mmcif_single_write()
254 return -EIO; in sh_mmcif_single_write()
257 host->wait_int = 0; in sh_mmcif_single_write()
258 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); in sh_mmcif_single_write()
261 if (time == 0 || host->sd_error != 0) in sh_mmcif_single_write()
264 host->wait_int = 0; in sh_mmcif_single_write()
266 sh_mmcif_read(&host->regs->ce_block_set)) + 3; in sh_mmcif_single_write()
268 sh_mmcif_write(*p++, &host->regs->ce_data); in sh_mmcif_single_write()
271 sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask); in sh_mmcif_single_write()
274 if (time == 0 || host->sd_error != 0) in sh_mmcif_single_write()
277 host->wait_int = 0; in sh_mmcif_single_write()
286 const unsigned long *p = (unsigned long *)data->dest; in sh_mmcif_multi_write()
290 return -EIO; in sh_mmcif_multi_write()
293 host->wait_int = 0; in sh_mmcif_multi_write()
294 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); in sh_mmcif_multi_write()
295 for (j = 0; j < data->blocks; j++) { in sh_mmcif_multi_write()
296 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); in sh_mmcif_multi_write()
300 if (time == 0 || host->sd_error != 0) in sh_mmcif_multi_write()
303 host->wait_int = 0; in sh_mmcif_multi_write()
305 sh_mmcif_write(*p++, &host->regs->ce_data); in sh_mmcif_multi_write()
315 if (cmd->resp_type & MMC_RSP_136) { in sh_mmcif_get_response()
316 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3); in sh_mmcif_get_response()
317 cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2); in sh_mmcif_get_response()
318 cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1); in sh_mmcif_get_response()
319 cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0); in sh_mmcif_get_response()
320 debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0], in sh_mmcif_get_response()
321 cmd->response[1], cmd->response[2], cmd->response[3]); in sh_mmcif_get_response()
323 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0); in sh_mmcif_get_response()
330 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12); in sh_mmcif_get_cmd12response()
337 u32 opc = cmd->cmdidx; in sh_mmcif_set_cmd()
340 switch (cmd->resp_type) { in sh_mmcif_set_cmd()
362 if (host->data) { in sh_mmcif_set_cmd()
364 switch (host->bus_width) { in sh_mmcif_set_cmd()
387 sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set); in sh_mmcif_set_cmd()
425 ret = -EINVAL; in sh_mmcif_data_trans()
436 u32 opc = cmd->cmdidx; in sh_mmcif_start_cmd()
439 /* MMCIF sends the STOP command automatically */ in sh_mmcif_start_cmd()
440 if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK) in sh_mmcif_start_cmd()
442 &host->regs->ce_int_mask); in sh_mmcif_start_cmd()
445 &host->regs->ce_int_mask); in sh_mmcif_start_cmd()
448 if (time == 0 || host->sd_error != 0) in sh_mmcif_start_cmd()
464 if (host->data) { in sh_mmcif_start_cmd()
465 sh_mmcif_write(0, &host->regs->ce_block_set); in sh_mmcif_start_cmd()
466 sh_mmcif_write(data->blocksize, &host->regs->ce_block_set); in sh_mmcif_start_cmd()
470 sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int); in sh_mmcif_start_cmd()
471 sh_mmcif_write(mask, &host->regs->ce_int_mask); in sh_mmcif_start_cmd()
473 debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg); in sh_mmcif_start_cmd()
475 sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg); in sh_mmcif_start_cmd()
476 host->wait_int = 0; in sh_mmcif_start_cmd()
478 sh_mmcif_write(opc, &host->regs->ce_cmd_set); in sh_mmcif_start_cmd()
484 if (host->sd_error) { in sh_mmcif_start_cmd()
485 switch (cmd->cmdidx) { in sh_mmcif_start_cmd()
489 ret = -ETIMEDOUT; in sh_mmcif_start_cmd()
492 printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx); in sh_mmcif_start_cmd()
496 host->sd_error = 0; in sh_mmcif_start_cmd()
497 host->wait_int = 0; in sh_mmcif_start_cmd()
505 if (host->wait_int == 1) { in sh_mmcif_start_cmd()
507 host->wait_int = 0; in sh_mmcif_start_cmd()
509 if (host->data) in sh_mmcif_start_cmd()
510 ret = sh_mmcif_data_trans(host, data, cmd->cmdidx); in sh_mmcif_start_cmd()
511 host->last_cmd = cmd->cmdidx; in sh_mmcif_start_cmd()
523 switch (cmd->cmdidx) { in sh_mmcif_send_cmd_common()
525 return -ETIMEDOUT; in sh_mmcif_send_cmd_common()
532 return -ETIMEDOUT; in sh_mmcif_send_cmd_common()
536 host->sd_error = 0; in sh_mmcif_send_cmd_common()
537 host->data = data; in sh_mmcif_send_cmd_common()
539 host->data = NULL; in sh_mmcif_send_cmd_common()
546 if (mmc->clock) in sh_mmcif_set_ios_common()
547 sh_mmcif_clock_control(host, mmc->clock); in sh_mmcif_set_ios_common()
549 if (mmc->bus_width == 8) in sh_mmcif_set_ios_common()
550 host->bus_width = MMC_BUS_WIDTH_8; in sh_mmcif_set_ios_common()
551 else if (mmc->bus_width == 4) in sh_mmcif_set_ios_common()
552 host->bus_width = MMC_BUS_WIDTH_4; in sh_mmcif_set_ios_common()
554 host->bus_width = MMC_BUS_WIDTH_1; in sh_mmcif_set_ios_common()
556 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); in sh_mmcif_set_ios_common()
564 sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); in sh_mmcif_initialize_common()
571 return (void *)mmc->priv; in mmc_priv()
618 return -ENOMEM; in mmcif_mmc_init()
621 host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; in mmcif_mmc_init()
622 host->clk = CONFIG_SH_MMCIF_CLK; in mmcif_mmc_init()
624 sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk); in mmcif_mmc_init()
625 sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk); in mmcif_mmc_init()
630 return -ENOMEM; in mmcif_mmc_init()
667 return mmc_bind(dev, &plat->mmc, &plat->cfg); in sh_mmcif_dm_bind()
681 return -EINVAL; in sh_mmcif_dm_probe()
683 host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K); in sh_mmcif_dm_probe()
684 if (!host->regs) in sh_mmcif_dm_probe()
685 return -ENOMEM; in sh_mmcif_dm_probe()
699 host->clk = clk_set_rate(&sh_mmcif_clk, 97500000); in sh_mmcif_dm_probe()
701 plat->cfg.name = dev->name; in sh_mmcif_dm_probe()
702 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; in sh_mmcif_dm_probe()
704 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", in sh_mmcif_dm_probe()
707 plat->cfg.host_caps |= MMC_MODE_8BIT; in sh_mmcif_dm_probe()
710 plat->cfg.host_caps |= MMC_MODE_4BIT; in sh_mmcif_dm_probe()
715 dev_err(dev, "Invalid \"bus-width\" value\n"); in sh_mmcif_dm_probe()
716 return -EINVAL; in sh_mmcif_dm_probe()
721 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; in sh_mmcif_dm_probe()
722 plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk); in sh_mmcif_dm_probe()
723 plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk); in sh_mmcif_dm_probe()
724 plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; in sh_mmcif_dm_probe()
726 upriv->mmc = &plat->mmc; in sh_mmcif_dm_probe()
732 { .compatible = "renesas,sh-mmcif" },
737 .name = "sh-mmcif",