22 static void sdhci_reset(struct sdhci_host *host, u8 mask)  in sdhci_reset()  argument
28 	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);  in sdhci_reset()
29 	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {  in sdhci_reset()
40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)  in sdhci_cmd_done()  argument
46 			cmd->response[i] = sdhci_readl(host,  in sdhci_cmd_done()
49 				cmd->response[i] |= sdhci_readb(host,  in sdhci_cmd_done()
53 		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);  in sdhci_cmd_done()
57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)  in sdhci_transfer_pio()  argument
64 			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);  in sdhci_transfer_pio()
66 			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);  in sdhci_transfer_pio()
70 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,  in sdhci_transfer_data()  argument
77 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);  in sdhci_transfer_data()
79 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);  in sdhci_transfer_data()
86 		stat = sdhci_readl(host, SDHCI_INT_STATUS);  in sdhci_transfer_data()
93 			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))  in sdhci_transfer_data()
95 			sdhci_writel(host, rdy, SDHCI_INT_STATUS);  in sdhci_transfer_data()
96 			sdhci_transfer_pio(host, data);  in sdhci_transfer_data()
109 			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);  in sdhci_transfer_data()
112 			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);  in sdhci_transfer_data()
147 	struct sdhci_host *host = mmc->priv;  local
168 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
184 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
212 		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
226 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
245 		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
248 		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
251 		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
252 		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
254 		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
257 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
264 	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
267 		stat = sdhci_readl(host, SDHCI_INT_STATUS);
272 			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
283 		sdhci_cmd_done(host, cmd);
284 		sdhci_writel(host, mask, SDHCI_INT_STATUS);
289 		ret = sdhci_transfer_data(host, data, start_addr);
291 	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
294 	stat = sdhci_readl(host, SDHCI_INT_STATUS);
295 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
297 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
303 	sdhci_reset(host, SDHCI_RESET_CMD);
304 	sdhci_reset(host, SDHCI_RESET_DATA);
316 	struct sdhci_host *host = mmc->priv;  local
320 	if (host->ops && host->ops->platform_execute_tuning) {
321 		err = host->ops->platform_execute_tuning(mmc, opcode);
331 	struct sdhci_host *host = mmc->priv;  local
336 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
348 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
353 	if (host->ops && host->ops->set_delay)
354 		host->ops->set_delay(host);
356 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
358 		 * Check if the Host Controller supports Programmable Clock
361 		if (host->clk_mul) {
363 				if ((host->max_clk / div) <= clock)
375 			if (host->max_clk <= clock) {
381 					if ((host->max_clk / div) <= clock)
390 			if ((host->max_clk / div) <= clock)
396 	if (host->ops && host->ops->set_clock)
397 		host->ops->set_clock(host, div);
403 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
407 	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
419 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
423 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)  argument
444 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
450 	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
464 	struct sdhci_host *host = mmc->priv;  local
466 	if (host->ops && host->ops->set_control_reg)
467 		host->ops->set_control_reg(host);
469 	if (mmc->clock != host->clock)
477 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
478 	gen_addr = (u32)host->ioaddr;
482 		if((u32)host->ioaddr & 0x100)
495 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
498 		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
499 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
502 		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
503 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
516 	if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
517 	    (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
520 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
522 	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)) {
523 		ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL_2);
525 		ctrl_2 |= host->mmc->drv_type << SDHCI_DRIVER_STRENGTH_SHIFT;
526 		sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL_2);
530 	if (host->ops && host->ops->set_ios_post)
531 		host->ops->set_ios_post(host);
538 	struct sdhci_host *host = mmc->priv;  local
540 	sdhci_reset(host, SDHCI_RESET_ALL);
542 	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
551 	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
553 	if (host->ops && host->ops->get_cd)
554 		host->ops->get_cd(host);
557 	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
560 	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
588 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,  argument
593 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
602 	if (host->quirks & SDHCI_QUIRK_REG32_RW)
603 		host->version =
604 			sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
606 		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
608 	cfg->name = host->name;
614 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
615 		caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
616 		host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
620 	if (host->max_clk == 0) {
621 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
622 			host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
625 			host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
627 		host->max_clk *= 1000000;
628 		if (host->clk_mul)
629 			host->max_clk *= host->clk_mul;
631 	if (host->max_clk == 0) {
636 	if (f_max && (f_max < host->max_clk))
639 		cfg->f_max = host->max_clk;
643 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
656 	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
657 		cfg->voltages |= host->voltages;
661 	/* Since Host Controller Version3.0 */
662 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
667 	if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
672 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
673 		caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
676 	    (host->quirks & SDHCI_QUIRK_NO_1_8_V))
698 	if (host->host_caps)
699 		cfg->host_caps |= host->host_caps;
712 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)  argument
716 	ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
720 	host->mmc = mmc_create(&host->cfg, host);
721 	if (host->mmc == NULL) {