drivers/mmc/sdhci-cadence.c

1 // SPDX-License-Identifier: GPL-2.0+
14 #include <mmc.h>
17 /* HRS - Host Register Set (specific to Cadence) */
18 #define SDHCI_CDNS_HRS04		0x10		/* PHY access port */
37 /* SRS - Slot Register Set (SDHCI-compatible) */
40 /* PHY */
55  * The tuned val register is 6 bit-wide, but not the whole of the range is
56  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
63 	struct mmc mmc;  member
73 	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
74 	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
75 	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
76 	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
77 	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
78 	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
79 	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
80 	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
81 	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
82 	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
83 	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
89 	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;  in sdhci_cdns_write_phy_reg()
134 	struct mmc *mmc = host->mmc;  in sdhci_cdns_set_control_reg()  local
135 	struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);  in sdhci_cdns_set_control_reg()
136 	unsigned int clock = mmc->clock;  in sdhci_cdns_set_control_reg()
142 	 * U-Boot does not support timing.  Use the clock frequency instead.  in sdhci_cdns_set_control_reg()
147 		if (mmc->ddr_mode)  in sdhci_cdns_set_control_reg()
152 		if (mmc->ddr_mode)  in sdhci_cdns_set_control_reg()
158 	tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_set_control_reg()
161 	writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_set_control_reg()
171 	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;  in sdhci_cdns_set_tune_val()
175 		return -EINVAL;  in sdhci_cdns_set_tune_val()
191 	struct mmc *mmc = &plat->mmc;  in sdhci_cdns_execute_tuning()  local
202 	if (!IS_MMC(mmc))  in sdhci_cdns_execute_tuning()
203 		return -ENOTSUPP;  in sdhci_cdns_execute_tuning()
206 		return -EINVAL;  in sdhci_cdns_execute_tuning()
210 		    mmc_send_tuning(mmc, opcode, NULL)) { /* bad */  in sdhci_cdns_execute_tuning()
223 		return -EIO;  in sdhci_cdns_execute_tuning()
226 	return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);  in sdhci_cdns_execute_tuning()
235 	return sdhci_bind(dev, &plat->mmc, &plat->cfg);  in sdhci_cdns_bind()
249 		return -EINVAL;  in sdhci_cdns_probe()
251 	plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);  in sdhci_cdns_probe()
252 	if (!plat->hrs_addr)  in sdhci_cdns_probe()
253 		return -ENOMEM;  in sdhci_cdns_probe()
255 	host->name = dev->name;  in sdhci_cdns_probe()
256 	host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;  in sdhci_cdns_probe()
257 	host->ops = &sdhci_cdns_ops;  in sdhci_cdns_probe()
258 	host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;  in sdhci_cdns_probe()
264 	ret = mmc_of_parse(dev, &plat->cfg);  in sdhci_cdns_probe()
268 	ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));  in sdhci_cdns_probe()
272 	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);  in sdhci_cdns_probe()
276 	upriv->mmc = &plat->mmc;  in sdhci_cdns_probe()
277 	host->mmc = &plat->mmc;  in sdhci_cdns_probe()
278 	host->mmc->priv = host;  in sdhci_cdns_probe()
284 	{ .compatible = "socionext,uniphier-sd4hc" },
290 	.name = "sdhci-cdns",