Lines Matching +full:no +full:- +full:mmc
4 * Sukumar Ghorai <s-ghorai@ti.com>
22 * MA 02111-1307 USA
29 #include <mmc.h>
163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) in omap_hsmmc_get_data() argument
166 return dev_get_priv(mmc->dev); in omap_hsmmc_get_data()
168 return (struct omap_hsmmc_data *)mmc->priv; in omap_hsmmc_get_data()
171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) in omap_hsmmc_get_cfg() argument
174 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); in omap_hsmmc_get_cfg()
175 return &plat->cfg; in omap_hsmmc_get_cfg()
177 return &((struct omap_hsmmc_data *)mmc->priv)->cfg; in omap_hsmmc_get_cfg()
188 return -1; in omap_mmc_setup_gpio_in()
202 static unsigned char mmc_board_init(struct mmc *mmc) in mmc_board_init() argument
205 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); in mmc_board_init()
213 pbias_lite = readl(&t2_base->pbias_lite); in mmc_board_init()
230 writel(pbias_lite, &t2_base->pbias_lite); in mmc_board_init()
234 &t2_base->pbias_lite); in mmc_board_init()
243 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, in mmc_board_init()
244 &t2_base->devconf0); in mmc_board_init()
246 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, in mmc_board_init()
247 &t2_base->devconf1); in mmc_board_init()
250 if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) in mmc_board_init()
251 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, in mmc_board_init()
252 &t2_base->ctl_prog_io1); in mmc_board_init()
254 writel(readl(&prcm_base->fclken1_core) | in mmc_board_init()
256 &prcm_base->fclken1_core); in mmc_board_init()
258 writel(readl(&prcm_base->iclken1_core) | in mmc_board_init()
260 &prcm_base->iclken1_core); in mmc_board_init()
266 if (mmc_get_blk_desc(mmc)->devnum == 0) in mmc_board_init()
277 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
279 writel(MMC_CMD0, &mmc_base->cmd); in mmc_init_stream()
281 while (!(readl(&mmc_base->stat) & CC_MASK)) { in mmc_init_stream()
282 if (get_timer(0) - start > MAX_RETRY_MS) { in mmc_init_stream()
287 writel(CC_MASK, &mmc_base->stat) in mmc_init_stream()
289 writel(MMC_CMD0, &mmc_base->cmd) in mmc_init_stream()
292 while (!(readl(&mmc_base->stat) & CC_MASK)) { in mmc_init_stream()
293 if (get_timer(0) - start > MAX_RETRY_MS) { in mmc_init_stream()
298 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
303 static void omap_hsmmc_io_recalibrate(struct mmc *mmc) in omap_hsmmc_io_recalibrate() argument
305 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_io_recalibrate()
308 switch (priv->mode) { in omap_hsmmc_io_recalibrate()
310 pinctrl_state = priv->hs200_1_8v_pinctrl_state; in omap_hsmmc_io_recalibrate()
313 pinctrl_state = priv->sdr104_pinctrl_state; in omap_hsmmc_io_recalibrate()
316 pinctrl_state = priv->sdr50_pinctrl_state; in omap_hsmmc_io_recalibrate()
319 pinctrl_state = priv->ddr50_pinctrl_state; in omap_hsmmc_io_recalibrate()
322 pinctrl_state = priv->sdr25_pinctrl_state; in omap_hsmmc_io_recalibrate()
325 pinctrl_state = priv->sdr12_pinctrl_state; in omap_hsmmc_io_recalibrate()
330 pinctrl_state = priv->hs_pinctrl_state; in omap_hsmmc_io_recalibrate()
333 pinctrl_state = priv->ddr_1_8v_pinctrl_state; in omap_hsmmc_io_recalibrate()
335 pinctrl_state = priv->default_pinctrl_state; in omap_hsmmc_io_recalibrate()
340 pinctrl_state = priv->default_pinctrl_state; in omap_hsmmc_io_recalibrate()
342 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) { in omap_hsmmc_io_recalibrate()
343 if (pinctrl_state->iodelay) in omap_hsmmc_io_recalibrate()
344 late_recalibrate_iodelay(pinctrl_state->padconf, in omap_hsmmc_io_recalibrate()
345 pinctrl_state->npads, in omap_hsmmc_io_recalibrate()
346 pinctrl_state->iodelay, in omap_hsmmc_io_recalibrate()
347 pinctrl_state->niodelays); in omap_hsmmc_io_recalibrate()
349 do_set_mux32((*ctrl)->control_padconf_core_base, in omap_hsmmc_io_recalibrate()
350 pinctrl_state->padconf, in omap_hsmmc_io_recalibrate()
351 pinctrl_state->npads); in omap_hsmmc_io_recalibrate()
355 static void omap_hsmmc_set_timing(struct mmc *mmc) in omap_hsmmc_set_timing() argument
359 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_set_timing()
361 mmc_base = priv->base_addr; in omap_hsmmc_set_timing()
364 val = readl(&mmc_base->ac12); in omap_hsmmc_set_timing()
366 priv->mode = mmc->selected_mode; in omap_hsmmc_set_timing()
368 if (mmc_is_mode_ddr(priv->mode)) in omap_hsmmc_set_timing()
369 writel(readl(&mmc_base->con) | DDR, &mmc_base->con); in omap_hsmmc_set_timing()
371 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); in omap_hsmmc_set_timing()
373 switch (priv->mode) { in omap_hsmmc_set_timing()
400 writel(val, &mmc_base->ac12); in omap_hsmmc_set_timing()
403 omap_hsmmc_io_recalibrate(mmc); in omap_hsmmc_set_timing()
408 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage) in omap_hsmmc_conf_bus_power() argument
411 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_conf_bus_power()
414 mmc_base = priv->base_addr; in omap_hsmmc_conf_bus_power()
416 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK; in omap_hsmmc_conf_bus_power()
417 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN; in omap_hsmmc_conf_bus_power()
429 writel(hctl, &mmc_base->hctl); in omap_hsmmc_conf_bus_power()
430 writel(ac12, &mmc_base->ac12); in omap_hsmmc_conf_bus_power()
436 int ret = -ETIMEDOUT; in omap_hsmmc_wait_dat0()
441 struct hsmmc *mmc_base = priv->base_addr; in omap_hsmmc_wait_dat0()
443 con = readl(&mmc_base->con); in omap_hsmmc_wait_dat0()
444 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con); in omap_hsmmc_wait_dat0()
447 while (timeout--) { in omap_hsmmc_wait_dat0()
448 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0); in omap_hsmmc_wait_dat0()
455 writel(con, &mmc_base->con); in omap_hsmmc_wait_dat0()
463 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV) in omap_hsmmc_set_io_regulator() argument
468 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_set_io_regulator()
470 if (!mmc->vqmmc_supply) in omap_hsmmc_set_io_regulator()
474 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false); in omap_hsmmc_set_io_regulator()
479 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false); in omap_hsmmc_set_io_regulator()
483 ret = regulator_set_value(mmc->vqmmc_supply, uV); in omap_hsmmc_set_io_regulator()
487 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true); in omap_hsmmc_set_io_regulator()
492 ret = regulator_set_value(priv->pbias_supply, uV); in omap_hsmmc_set_io_regulator()
493 if (ret && ret != -ENOSYS) in omap_hsmmc_set_io_regulator()
496 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true); in omap_hsmmc_set_io_regulator()
504 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc) in omap_hsmmc_set_signal_voltage() argument
506 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_set_signal_voltage()
507 struct hsmmc *mmc_base = priv->base_addr; in omap_hsmmc_set_signal_voltage()
508 int mv = mmc_voltage_to_mv(mmc->signal_voltage); in omap_hsmmc_set_signal_voltage()
514 return -EINVAL; in omap_hsmmc_set_signal_voltage()
516 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { in omap_hsmmc_set_signal_voltage()
521 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { in omap_hsmmc_set_signal_voltage()
525 return -EOPNOTSUPP; in omap_hsmmc_set_signal_voltage()
528 val = readl(&mmc_base->capa); in omap_hsmmc_set_signal_voltage()
530 return -EOPNOTSUPP; in omap_hsmmc_set_signal_voltage()
532 priv->signal_voltage = mmc->signal_voltage; in omap_hsmmc_set_signal_voltage()
534 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage); in omap_hsmmc_set_signal_voltage()
537 return omap_hsmmc_set_io_regulator(mmc, mv); in omap_hsmmc_set_signal_voltage()
540 if (mmc_get_blk_desc(mmc)->devnum == 0) in omap_hsmmc_set_signal_voltage()
549 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc) in omap_hsmmc_set_capabilities() argument
552 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_set_capabilities()
555 mmc_base = priv->base_addr; in omap_hsmmc_set_capabilities()
556 val = readl(&mmc_base->capa); in omap_hsmmc_set_capabilities()
558 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { in omap_hsmmc_set_capabilities()
560 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) { in omap_hsmmc_set_capabilities()
568 writel(val, &mmc_base->capa); in omap_hsmmc_set_capabilities()
574 static void omap_hsmmc_disable_tuning(struct mmc *mmc) in omap_hsmmc_disable_tuning() argument
577 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_disable_tuning()
580 mmc_base = priv->base_addr; in omap_hsmmc_disable_tuning()
581 val = readl(&mmc_base->ac12); in omap_hsmmc_disable_tuning()
583 writel(val, &mmc_base->ac12); in omap_hsmmc_disable_tuning()
585 val = readl(&mmc_base->dll); in omap_hsmmc_disable_tuning()
587 writel(val, &mmc_base->dll); in omap_hsmmc_disable_tuning()
590 static void omap_hsmmc_set_dll(struct mmc *mmc, int count) in omap_hsmmc_set_dll() argument
594 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_set_dll()
597 mmc_base = priv->base_addr; in omap_hsmmc_set_dll()
598 val = readl(&mmc_base->dll); in omap_hsmmc_set_dll()
602 writel(val, &mmc_base->dll); in omap_hsmmc_set_dll()
605 writel(val, &mmc_base->dll); in omap_hsmmc_set_dll()
607 if (readl(&mmc_base->dll) & DLL_CALIB) in omap_hsmmc_set_dll()
611 writel(val, &mmc_base->dll); in omap_hsmmc_set_dll()
618 struct mmc *mmc = upriv->mmc; in omap_hsmmc_execute_tuning() local
631 mmc_base = priv->base_addr; in omap_hsmmc_execute_tuning()
632 val = readl(&mmc_base->capa2); in omap_hsmmc_execute_tuning()
635 if (!((mmc->selected_mode == MMC_HS_200) || in omap_hsmmc_execute_tuning()
636 (mmc->selected_mode == UHS_SDR104) || in omap_hsmmc_execute_tuning()
637 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) in omap_hsmmc_execute_tuning()
650 val = readl(&mmc_base->dll); in omap_hsmmc_execute_tuning()
652 writel(val, &mmc_base->dll); in omap_hsmmc_execute_tuning()
660 omap_hsmmc_set_dll(mmc, phase_delay); in omap_hsmmc_execute_tuning()
662 cur_match = !mmc_send_tuning(mmc, opcode, NULL); in omap_hsmmc_execute_tuning()
689 ret = -EIO; in omap_hsmmc_execute_tuning()
693 val = readl(&mmc_base->ac12); in omap_hsmmc_execute_tuning()
695 ret = -EIO; in omap_hsmmc_execute_tuning()
702 if (temperature < -20000) in omap_hsmmc_execute_tuning()
703 phase_delay = min(max_window + 4 * max_len - 24, in omap_hsmmc_execute_tuning()
722 * +2 to -10 range. If found, move away from it in the appropriate in omap_hsmmc_execute_tuning()
726 omap_hsmmc_set_dll(mmc, phase_delay + i); in omap_hsmmc_execute_tuning()
727 if (mmc_send_tuning(mmc, opcode, NULL)) { in omap_hsmmc_execute_tuning()
731 phase_delay += i - 12; in omap_hsmmc_execute_tuning()
733 phase_delay += i - 8; in omap_hsmmc_execute_tuning()
735 phase_delay += i - 6; in omap_hsmmc_execute_tuning()
737 phase_delay += i - 6; in omap_hsmmc_execute_tuning()
743 for (i = 2; i >= -10; i--) { in omap_hsmmc_execute_tuning()
744 omap_hsmmc_set_dll(mmc, phase_delay + i); in omap_hsmmc_execute_tuning()
745 if (mmc_send_tuning(mmc, opcode, NULL)) { in omap_hsmmc_execute_tuning()
763 omap_hsmmc_set_dll(mmc, phase_delay); in omap_hsmmc_execute_tuning()
772 omap_hsmmc_disable_tuning(mmc); in omap_hsmmc_execute_tuning()
783 struct hsmmc *mmc_base = priv->base_addr; in omap_hsmmc_send_init_stream()
789 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) in mmc_enable_irq() argument
791 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in mmc_enable_irq()
792 struct hsmmc *mmc_base = priv->base_addr; in mmc_enable_irq()
802 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx)) in mmc_enable_irq()
805 writel(irq_mask, &mmc_base->ie); in mmc_enable_irq()
808 static int omap_hsmmc_init_setup(struct mmc *mmc) in omap_hsmmc_init_setup() argument
810 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_init_setup()
816 mmc_base = priv->base_addr; in omap_hsmmc_init_setup()
817 mmc_board_init(mmc); in omap_hsmmc_init_setup()
819 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, in omap_hsmmc_init_setup()
820 &mmc_base->sysconfig); in omap_hsmmc_init_setup()
822 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { in omap_hsmmc_init_setup()
823 if (get_timer(0) - start > MAX_RETRY_MS) { in omap_hsmmc_init_setup()
825 return -ETIMEDOUT; in omap_hsmmc_init_setup()
828 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); in omap_hsmmc_init_setup()
830 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { in omap_hsmmc_init_setup()
831 if (get_timer(0) - start > MAX_RETRY_MS) { in omap_hsmmc_init_setup()
834 return -ETIMEDOUT; in omap_hsmmc_init_setup()
838 reg_val = readl(&mmc_base->hl_hwinfo); in omap_hsmmc_init_setup()
840 priv->controller_flags |= OMAP_HSMMC_USE_ADMA; in omap_hsmmc_init_setup()
844 reg_val = omap_hsmmc_set_capabilities(mmc); in omap_hsmmc_init_setup()
845 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ? in omap_hsmmc_init_setup()
848 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); in omap_hsmmc_init_setup()
849 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, in omap_hsmmc_init_setup()
850 &mmc_base->capa); in omap_hsmmc_init_setup()
853 reg_val = readl(&mmc_base->con) & RESERVED_MASK; in omap_hsmmc_init_setup()
857 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); in omap_hsmmc_init_setup()
860 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), in omap_hsmmc_init_setup()
862 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, in omap_hsmmc_init_setup()
865 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { in omap_hsmmc_init_setup()
866 if (get_timer(0) - start > MAX_RETRY_MS) { in omap_hsmmc_init_setup()
868 return -ETIMEDOUT; in omap_hsmmc_init_setup()
871 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); in omap_hsmmc_init_setup()
873 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); in omap_hsmmc_init_setup()
875 mmc_enable_irq(mmc, NULL); in omap_hsmmc_init_setup()
885 * MMC controller internal finite state machine reset
894 mmc_reg_out(&mmc_base->sysctl, bit, bit); in mmc_reset_controller_fsm()
912 if (!(readl(&mmc_base->sysctl) & bit)) { in mmc_reset_controller_fsm()
914 while (!(readl(&mmc_base->sysctl) & bit)) { in mmc_reset_controller_fsm()
915 if (get_timer(0) - start > MMC_TIMEOUT_MS) in mmc_reset_controller_fsm()
921 while ((readl(&mmc_base->sysctl) & bit) != 0) { in mmc_reset_controller_fsm()
922 if (get_timer(0) - start > MAX_RETRY_MS) { in mmc_reset_controller_fsm()
931 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) in omap_hsmmc_adma_desc() argument
933 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_adma_desc()
937 desc = &priv->adma_desc_table[priv->desc_slot]; in omap_hsmmc_adma_desc()
941 priv->desc_slot++; in omap_hsmmc_adma_desc()
945 desc->len = len; in omap_hsmmc_adma_desc()
946 desc->addr = (u32)buf; in omap_hsmmc_adma_desc()
947 desc->reserved = 0; in omap_hsmmc_adma_desc()
948 desc->attr = attr; in omap_hsmmc_adma_desc()
951 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc, in omap_hsmmc_prepare_adma_table() argument
954 uint total_len = data->blocksize * data->blocks; in omap_hsmmc_prepare_adma_table()
956 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_prepare_adma_table()
960 priv->desc_slot = 0; in omap_hsmmc_prepare_adma_table()
961 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *) in omap_hsmmc_prepare_adma_table()
965 if (data->flags & MMC_DATA_READ) in omap_hsmmc_prepare_adma_table()
966 buf = data->dest; in omap_hsmmc_prepare_adma_table()
968 buf = (char *)data->src; in omap_hsmmc_prepare_adma_table()
970 while (--i) { in omap_hsmmc_prepare_adma_table()
971 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false); in omap_hsmmc_prepare_adma_table()
973 total_len -= ADMA_MAX_LEN; in omap_hsmmc_prepare_adma_table()
976 omap_hsmmc_adma_desc(mmc, buf, total_len, true); in omap_hsmmc_prepare_adma_table()
978 flush_dcache_range((long)priv->adma_desc_table, in omap_hsmmc_prepare_adma_table()
979 (long)priv->adma_desc_table + in omap_hsmmc_prepare_adma_table()
985 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data) in omap_hsmmc_prepare_data() argument
988 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_prepare_data()
992 mmc_base = priv->base_addr; in omap_hsmmc_prepare_data()
993 omap_hsmmc_prepare_adma_table(mmc, data); in omap_hsmmc_prepare_data()
995 if (data->flags & MMC_DATA_READ) in omap_hsmmc_prepare_data()
996 buf = data->dest; in omap_hsmmc_prepare_data()
998 buf = (char *)data->src; in omap_hsmmc_prepare_data()
1000 val = readl(&mmc_base->hctl); in omap_hsmmc_prepare_data()
1002 writel(val, &mmc_base->hctl); in omap_hsmmc_prepare_data()
1004 val = readl(&mmc_base->con); in omap_hsmmc_prepare_data()
1006 writel(val, &mmc_base->con); in omap_hsmmc_prepare_data()
1008 writel((u32)priv->adma_desc_table, &mmc_base->admasal); in omap_hsmmc_prepare_data()
1012 ROUND(data->blocksize * data->blocks, in omap_hsmmc_prepare_data()
1016 static void omap_hsmmc_dma_cleanup(struct mmc *mmc) in omap_hsmmc_dma_cleanup() argument
1019 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_dma_cleanup()
1022 mmc_base = priv->base_addr; in omap_hsmmc_dma_cleanup()
1024 val = readl(&mmc_base->con); in omap_hsmmc_dma_cleanup()
1026 writel(val, &mmc_base->con); in omap_hsmmc_dma_cleanup()
1028 val = readl(&mmc_base->hctl); in omap_hsmmc_dma_cleanup()
1030 writel(val, &mmc_base->hctl); in omap_hsmmc_dma_cleanup()
1032 kfree(priv->adma_desc_table); in omap_hsmmc_dma_cleanup()
1042 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, argument
1045 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1052 struct mmc *mmc = upriv->mmc;
1057 priv->last_cmd = cmd->cmdidx;
1059 mmc_base = priv->base_addr;
1061 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1065 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1066 if (get_timer(0) - start > MAX_RETRY_MS) {
1069 return -ETIMEDOUT;
1072 writel(0xFFFFFFFF, &mmc_base->stat);
1074 while (readl(&mmc_base->stat)) {
1075 if (get_timer(0) - start > MAX_RETRY_MS) {
1077 __func__, readl(&mmc_base->stat));
1078 return -ETIMEDOUT;
1088 * 00 = No Response
1094 * retry not supported by mmc.c(core file)
1096 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1099 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1101 else if (cmd->resp_type & MMC_RSP_136)
1103 else if (cmd->resp_type & MMC_RSP_BUSY)
1113 if (cmd->resp_type & MMC_RSP_CRC)
1115 if (cmd->resp_type & MMC_RSP_OPCODE)
1119 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1120 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1122 data->blocksize = 512;
1123 writel(data->blocksize | (data->blocks << 16),
1124 &mmc_base->blk);
1126 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1128 if (data->flags & MMC_DATA_READ)
1134 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1135 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1136 omap_hsmmc_prepare_data(mmc, data);
1142 mmc_enable_irq(mmc, cmd);
1144 writel(cmd->cmdarg, &mmc_base->arg);
1145 udelay(20); /* To fix "No status update" error on eMMC */
1146 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1150 mmc_stat = readl(&mmc_base->stat);
1152 printf("%s : timeout: No status update\n", __func__);
1153 return -ETIMEDOUT;
1159 return -ETIMEDOUT;
1161 return -1;
1164 writel(CC_MASK, &mmc_base->stat);
1165 if (cmd->resp_type & MMC_RSP_PRESENT) {
1166 if (cmd->resp_type & MMC_RSP_136) {
1168 cmd->response[3] = readl(&mmc_base->rsp10);
1169 cmd->response[2] = readl(&mmc_base->rsp32);
1170 cmd->response[1] = readl(&mmc_base->rsp54);
1171 cmd->response[0] = readl(&mmc_base->rsp76);
1174 cmd->response[0] = readl(&mmc_base->rsp10);
1179 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1180 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1184 omap_hsmmc_dma_cleanup(mmc);
1185 return -EIO;
1188 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1195 mmc_stat = readl(&mmc_base->stat);
1197 writel(readl(&mmc_base->stat) | TC_MASK,
1198 &mmc_base->stat);
1202 printf("%s : DMA timeout: No status update\n",
1204 return -ETIMEDOUT;
1208 omap_hsmmc_dma_cleanup(mmc);
1213 if (data && (data->flags & MMC_DATA_READ)) {
1214 mmc_read_data(mmc_base, data->dest,
1215 data->blocksize * data->blocks);
1216 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1217 mmc_write_data(mmc_base, data->src,
1218 data->blocksize * data->blocks);
1238 mmc_stat = readl(&mmc_base->stat);
1239 if (get_timer(0) - start > MAX_RETRY_MS) {
1242 return -ETIMEDOUT;
1255 writel(readl(&mmc_base->stat) | BRR_MASK,
1256 &mmc_base->stat);
1258 *output_buf = readl(&mmc_base->data);
1261 size -= (count*4);
1265 writel(readl(&mmc_base->stat) | BWR_MASK,
1266 &mmc_base->stat);
1269 writel(readl(&mmc_base->stat) | TC_MASK,
1270 &mmc_base->stat);
1294 mmc_stat = readl(&mmc_base->stat);
1295 if (get_timer(0) - start > MAX_RETRY_MS) {
1298 return -ETIMEDOUT;
1311 writel(readl(&mmc_base->stat) | BWR_MASK,
1312 &mmc_base->stat);
1314 writel(*input_buf, &mmc_base->data);
1317 size -= (count*4);
1321 writel(readl(&mmc_base->stat) | BRR_MASK,
1322 &mmc_base->stat);
1325 writel(readl(&mmc_base->stat) | TC_MASK,
1326 &mmc_base->stat);
1336 return -ENOTSUPP;
1341 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1346 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1349 static void omap_hsmmc_set_clock(struct mmc *mmc) argument
1351 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1356 mmc_base = priv->base_addr;
1360 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1363 if (mmc->clock != 0) {
1364 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1371 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1375 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1376 if (get_timer(0) - start > MAX_RETRY_MS) {
1382 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1383 mmc->clock = priv->clock;
1387 static void omap_hsmmc_set_bus_width(struct mmc *mmc) argument
1389 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1392 mmc_base = priv->base_addr;
1394 switch (mmc->bus_width) {
1396 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1397 &mmc_base->con);
1401 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1402 &mmc_base->con);
1403 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1404 &mmc_base->hctl);
1409 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1410 &mmc_base->con);
1411 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1412 &mmc_base->hctl);
1416 priv->bus_width = mmc->bus_width;
1420 static int omap_hsmmc_set_ios(struct mmc *mmc) argument
1422 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1428 struct mmc *mmc = upriv->mmc;
1430 struct hsmmc *mmc_base = priv->base_addr;
1433 if (priv->bus_width != mmc->bus_width)
1434 omap_hsmmc_set_bus_width(mmc);
1436 if (priv->clock != mmc->clock)
1437 omap_hsmmc_set_clock(mmc);
1439 if (mmc->clk_disable)
1445 if (priv->mode != mmc->selected_mode)
1446 omap_hsmmc_set_timing(mmc);
1449 if (priv->signal_voltage != mmc->signal_voltage)
1450 ret = omap_hsmmc_set_signal_voltage(mmc);
1460 int value = -1;
1463 value = dm_gpio_get_value(&priv->cd_gpio);
1465 /* if no CD return as 1 */
1477 value = dm_gpio_get_value(&priv->wp_gpio);
1479 /* if no WP return as 0 */
1485 static int omap_hsmmc_getcd(struct mmc *mmc) argument
1487 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1490 /* if no CD return as 1 */
1491 cd_gpio = priv->cd_gpio;
1495 /* NOTE: assumes card detect signal is active-low */
1499 static int omap_hsmmc_getwp(struct mmc *mmc) argument
1501 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1504 /* if no WP return as 0 */
1505 wp_gpio = priv->wp_gpio;
1509 /* NOTE: assumes write protect signal is active-high */
1547 struct mmc *mmc; local
1554 return -1;
1560 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1564 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1569 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1576 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1578 /* Enable 8-bit interface for eMMC on DRA7XX */
1584 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1588 /* on error gpio values are set to -1, which is what we want */
1589 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1590 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1593 cfg = &priv->cfg;
1595 cfg->name = "OMAP SD/MMC";
1596 cfg->ops = &omap_hsmmc_ops;
1598 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1599 cfg->host_caps = host_caps_val & ~host_caps_mask;
1601 cfg->f_min = 400000;
1604 cfg->f_max = f_max;
1606 if (cfg->host_caps & MMC_MODE_HS) {
1607 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1608 cfg->f_max = 52000000;
1610 cfg->f_max = 26000000;
1612 cfg->f_max = 20000000;
1615 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1622 cfg->b_max = 1;
1625 mmc = mmc_create(cfg, priv);
1626 if (mmc == NULL)
1627 return -1;
1680 const void *fdt = gd->fdt_blob;
1700 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc, argument
1703 const void *fdt = gd->fdt_blob;
1705 int node = dev_of_offset(mmc->dev);
1716 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc, argument
1719 const void *fdt = gd->fdt_blob;
1723 int node = dev_of_offset(mmc->dev);
1731 /* No manual mode iodelay values if count < 2 */
1740 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads) argument
1748 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1750 return ERR_PTR(-EINVAL);
1752 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1755 return ERR_PTR(-EINVAL);
1760 return ERR_PTR(-EINVAL);
1768 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay) argument
1776 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1781 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1784 return ERR_PTR(-EINVAL);
1789 return ERR_PTR(-EINVAL);
1797 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode) argument
1802 const void *fdt = gd->fdt_blob;
1803 int node = dev_of_offset(mmc->dev);
1814 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1820 sprintf(prop_name, "pinctrl-%d", index);
1822 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1824 if (IS_ERR(pinctrl_state->padconf))
1826 pinctrl_state->npads = npads;
1828 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1830 if (IS_ERR(pinctrl_state->iodelay))
1832 pinctrl_state->niodelays = niodelays;
1837 kfree(pinctrl_state->padconf);
1848 if (!(cfg->host_caps & capmask)) \
1851 if (priv->hw_rev) { \
1852 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1853 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1857 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1860 debug("%s: no pinctrl for %s\n", \
1861 mmc->dev->name, #mode); \
1862 cfg->host_caps &= ~(capmask); \
1864 priv->mode##_pinctrl_state = s; \
1868 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) argument
1870 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1871 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1874 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1877 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1879 printf("no pinctrl state for default mode\n");
1880 return -EINVAL;
1883 priv->default_pinctrl_state = default_pinctrl;
1912 struct mmc_config *cfg = &plat->cfg;
1916 const void *fdt = gd->fdt_blob;
1920 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1928 if (!cfg->f_max)
1929 cfg->f_max = 52000000;
1930 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1931 cfg->f_min = 400000;
1932 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1933 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1934 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1935 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1936 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1937 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1939 plat->controller_flags |= of_data->controller_flags;
1944 plat->hw_rev = fixups->hw_rev;
1945 cfg->host_caps &= ~fixups->unsupported_caps;
1946 cfg->f_max = fixups->max_freq;
1959 plat->mmc = calloc(1, sizeof(struct mmc));
1960 return mmc_bind(dev, plat->mmc, &plat->cfg);
1968 struct mmc_config *cfg = &plat->cfg;
1969 struct mmc *mmc; local
1974 cfg->name = "OMAP SD/MMC";
1975 priv->base_addr = plat->base_addr;
1976 priv->controller_flags = plat->controller_flags;
1977 priv->hw_rev = plat->hw_rev;
1980 mmc = plat->mmc;
1982 mmc = mmc_create(cfg, priv);
1983 if (mmc == NULL)
1984 return -1;
1987 device_get_supply_regulator(dev, "pbias-supply",
1988 &priv->pbias_supply);
1992 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1993 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1997 mmc->dev = dev;
1998 upriv->mmc = mmc;
2001 ret = omap_hsmmc_get_pinctrl_state(mmc);
2007 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2008 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2009 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2014 return omap_hsmmc_init_setup(mmc);
2024 { .compatible = "ti,omap3-hsmmc" },
2025 { .compatible = "ti,omap4-hsmmc" },
2026 { .compatible = "ti,am33xx-hsmmc" },
2027 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },