Lines Matching +full:ck +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
268 /* whether to use gpio detection or built-in hw detection */
271 /* card detection / write protection GPIOs */
290 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST); in msdc_reset_hw()
292 readl_poll_timeout(&host->base->msdc_cfg, reg, in msdc_reset_hw()
300 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR); in msdc_fifo_clr()
302 readl_poll_timeout(&host->base->msdc_fifocs, reg, in msdc_fifo_clr()
308 return (readl(&host->base->msdc_fifocs) & in msdc_fifo_rx_bytes()
314 return (readl(&host->base->msdc_fifocs) & in msdc_fifo_tx_bytes()
322 switch (cmd->resp_type) { in msdc_cmd_find_resp()
349 u32 opcode = cmd->cmdidx; in msdc_cmd_prepare_raw_cmd()
373 if (data->flags == MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
376 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
379 blocksize = data->blocksize; in msdc_cmd_prepare_raw_cmd()
396 u32 *rsp = cmd->response; in msdc_cmd_done()
399 if (cmd->resp_type & MMC_RSP_PRESENT) { in msdc_cmd_done()
400 if (cmd->resp_type & MMC_RSP_136) { in msdc_cmd_done()
401 rsp[0] = readl(&host->base->sdc_resp[3]); in msdc_cmd_done()
402 rsp[1] = readl(&host->base->sdc_resp[2]); in msdc_cmd_done()
403 rsp[2] = readl(&host->base->sdc_resp[1]); in msdc_cmd_done()
404 rsp[3] = readl(&host->base->sdc_resp[0]); in msdc_cmd_done()
406 rsp[0] = readl(&host->base->sdc_resp[0]); in msdc_cmd_done()
411 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK && in msdc_cmd_done()
412 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200) in msdc_cmd_done()
420 ret = -ETIMEDOUT; in msdc_cmd_done()
422 ret = -EIO; in msdc_cmd_done()
434 ret = readl_poll_timeout(&host->base->sdc_sts, reg, in msdc_cmd_is_ready()
443 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) { in msdc_cmd_is_ready()
444 ret = readl_poll_timeout(&host->base->msdc_ps, reg, in msdc_cmd_is_ready()
466 return -EIO; in msdc_start_command()
470 host->last_resp_type = cmd->resp_type; in msdc_start_command()
471 host->last_data_write = 0; in msdc_start_command()
476 blocks = data->blocks; in msdc_start_command()
478 writel(CMD_INTS_MASK, &host->base->msdc_int); in msdc_start_command()
479 writel(blocks, &host->base->sdc_blk_num); in msdc_start_command()
480 writel(cmd->cmdarg, &host->base->sdc_arg); in msdc_start_command()
481 writel(rawcmd, &host->base->sdc_cmd); in msdc_start_command()
483 ret = readl_poll_timeout(&host->base->msdc_int, status, in msdc_start_command()
497 *buf++ = readb(&host->base->msdc_rxdata); in msdc_fifo_read()
498 size--; in msdc_fifo_read()
503 *wbuf++ = readl(&host->base->msdc_rxdata); in msdc_fifo_read()
504 size -= 4; in msdc_fifo_read()
509 *buf++ = readb(&host->base->msdc_rxdata); in msdc_fifo_read()
510 size--; in msdc_fifo_read()
519 writeb(*buf++, &host->base->msdc_txdata); in msdc_fifo_write()
520 size--; in msdc_fifo_write()
525 writel(*wbuf++, &host->base->msdc_txdata); in msdc_fifo_write()
526 size -= 4; in msdc_fifo_write()
531 writeb(*buf++, &host->base->msdc_txdata); in msdc_fifo_write()
532 size--; in msdc_fifo_write()
543 status = readl(&host->base->msdc_int); in msdc_pio_read()
544 writel(status, &host->base->msdc_int); in msdc_pio_read()
548 ret = -EIO; in msdc_pio_read()
553 ret = -ETIMEDOUT; in msdc_pio_read()
562 size -= chksz; in msdc_pio_read()
568 ret = -EIO; in msdc_pio_read()
585 status = readl(&host->base->msdc_int); in msdc_pio_write()
586 writel(status, &host->base->msdc_int); in msdc_pio_write()
590 ret = -EIO; in msdc_pio_write()
595 ret = -ETIMEDOUT; in msdc_pio_write()
602 ret = -EIO; in msdc_pio_write()
610 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) { in msdc_pio_write()
613 size -= chksz; in msdc_pio_write()
625 if (data->flags == MMC_DATA_WRITE) in msdc_start_data()
626 host->last_data_write = 1; in msdc_start_data()
628 writel(DATA_INTS_MASK, &host->base->msdc_int); in msdc_start_data()
630 size = data->blocks * data->blocksize; in msdc_start_data()
632 if (data->flags == MMC_DATA_WRITE) in msdc_start_data()
633 ret = msdc_pio_write(host, (const u8 *)data->src, size); in msdc_start_data()
635 ret = msdc_pio_read(host, (u8 *)data->dest, size); in msdc_start_data()
666 host->timeout_ns = ns; in msdc_set_timeout()
667 host->timeout_clks = clks; in msdc_set_timeout()
669 if (host->sclk == 0) { in msdc_set_timeout()
672 clk_ns = 1000000000UL / host->sclk; in msdc_set_timeout()
673 timeout = (ns + clk_ns - 1) / clk_ns + clks; in msdc_set_timeout()
675 timeout = (timeout + (0x1 << 20) - 1) >> 20; in msdc_set_timeout()
676 if (host->dev_comp->clk_div_bits == 8) in msdc_set_timeout()
677 mode = (readl(&host->base->msdc_cfg) & in msdc_set_timeout()
680 mode = (readl(&host->base->msdc_cfg) & in msdc_set_timeout()
684 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_set_timeout()
688 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, in msdc_set_timeout()
694 u32 val = readl(&host->base->sdc_cfg); in msdc_set_buswidth()
711 writel(val, &host->base->sdc_cfg); in msdc_set_buswidth()
722 host->mclk = 0; in msdc_set_mclk()
723 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); in msdc_set_mclk()
727 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
728 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
730 clrbits_le32(&host->base->msdc_cfg, in msdc_set_mclk()
740 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
742 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
744 div = (host->src_clk_freq + ((hz << 2) - 1)) / in msdc_set_mclk()
746 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
750 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
751 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
752 setbits_le32(&host->base->msdc_cfg, in msdc_set_mclk()
755 setbits_le32(&host->base->msdc_cfg, in msdc_set_mclk()
758 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
761 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
764 sclk = host->src_clk_freq; in msdc_set_mclk()
767 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
769 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
771 div = (host->src_clk_freq + ((hz << 2) - 1)) / in msdc_set_mclk()
773 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
777 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); in msdc_set_mclk()
779 if (host->dev_comp->clk_div_bits == 8) { in msdc_set_mclk()
781 clrsetbits_le32(&host->base->msdc_cfg, in msdc_set_mclk()
788 clrsetbits_le32(&host->base->msdc_cfg, in msdc_set_mclk()
794 readl_poll_timeout(&host->base->msdc_cfg, reg, in msdc_set_mclk()
797 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); in msdc_set_mclk()
798 host->sclk = sclk; in msdc_set_mclk()
799 host->mclk = hz; in msdc_set_mclk()
800 host->timing = timing; in msdc_set_mclk()
803 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
809 if (host->sclk <= 52000000) { in msdc_set_mclk()
810 writel(host->def_tune_para.iocon, &host->base->msdc_iocon); in msdc_set_mclk()
811 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
812 &host->base->pad_tune); in msdc_set_mclk()
814 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon); in msdc_set_mclk()
815 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
816 &host->base->pad_tune); in msdc_set_mclk()
819 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing); in msdc_set_mclk()
826 struct mmc *mmc = &plat->mmc; in msdc_ops_set_ios()
827 uint clock = mmc->clock; in msdc_ops_set_ios()
829 msdc_set_buswidth(host, mmc->bus_width); in msdc_ops_set_ios()
831 if (mmc->clk_disable) in msdc_ops_set_ios()
833 else if (clock < mmc->cfg->f_min) in msdc_ops_set_ios()
834 clock = mmc->cfg->f_min; in msdc_ops_set_ios()
836 if (host->mclk != clock || host->timing != mmc->selected_mode) in msdc_ops_set_ios()
837 msdc_set_mclk(host, mmc->selected_mode, clock); in msdc_ops_set_ios()
847 if (host->builtin_cd) { in msdc_ops_get_cd()
848 val = readl(&host->base->msdc_ps); in msdc_ops_get_cd()
853 if (!host->gpio_cd.dev) in msdc_ops_get_cd()
856 return dm_gpio_get_value(&host->gpio_cd); in msdc_ops_get_cd()
867 if (!host->gpio_wp.dev) in msdc_ops_get_wp()
870 return !dm_gpio_get_value(&host->gpio_wp); in msdc_ops_get_wp()
887 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { in get_delay_len()
892 return PAD_DELAY_MAX - start_bit; in get_delay_len()
939 struct mmc *mmc = &plat->mmc; in msdc_tune_response()
945 void __iomem *tune_reg = &host->base->pad_tune; in msdc_tune_response()
949 if (host->dev_comp->pad_tune0) in msdc_tune_response()
950 tune_reg = &host->base->pad_tune0; in msdc_tune_response()
952 if (mmc->selected_mode == MMC_HS_200 || in msdc_tune_response()
953 mmc->selected_mode == UHS_SDR104) in msdc_tune_response()
955 host->hs200_cmd_int_delay << in msdc_tune_response()
958 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); in msdc_tune_response()
981 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); in msdc_tune_response()
1002 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); in msdc_tune_response()
1008 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); in msdc_tune_response()
1015 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
1036 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
1043 struct mmc *mmc = &plat->mmc; in msdc_tune_data()
1047 void __iomem *tune_reg = &host->base->pad_tune; in msdc_tune_data()
1051 if (host->dev_comp->pad_tune0) in msdc_tune_data()
1052 tune_reg = &host->base->pad_tune0; in msdc_tune_data()
1054 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); in msdc_tune_data()
1055 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); in msdc_tune_data()
1077 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); in msdc_tune_data()
1078 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); in msdc_tune_data()
1100 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); in msdc_tune_data()
1101 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); in msdc_tune_data()
1107 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); in msdc_tune_data()
1108 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); in msdc_tune_data()
1115 if (mmc->selected_mode == MMC_HS_200 || in msdc_tune_data()
1116 mmc->selected_mode == UHS_SDR104) in msdc_tune_data()
1118 host->hs200_write_int_delay << in msdc_tune_data()
1123 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
1130 struct mmc *mmc = &plat->mmc; in msdc_execute_tuning()
1133 if (mmc->selected_mode == MMC_HS_400) { in msdc_execute_tuning()
1134 writel(host->hs400_ds_delay, &host->base->pad_ds_tune); in msdc_execute_tuning()
1136 clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS); in msdc_execute_tuning()
1137 host->hs400_mode = true; in msdc_execute_tuning()
1141 if (ret == -EIO) { in msdc_execute_tuning()
1146 if (!host->hs400_mode) { in msdc_execute_tuning()
1148 if (ret == -EIO) in msdc_execute_tuning()
1152 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon); in msdc_execute_tuning()
1153 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune); in msdc_execute_tuning()
1162 void __iomem *tune_reg = &host->base->pad_tune; in msdc_init_hw()
1164 if (host->dev_comp->pad_tune0) in msdc_init_hw()
1165 tune_reg = &host->base->pad_tune0; in msdc_init_hw()
1168 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE); in msdc_init_hw()
1171 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO); in msdc_init_hw()
1177 if (host->builtin_cd) in msdc_init_hw()
1178 clrsetbits_le32(&host->base->msdc_ps, in msdc_init_hw()
1183 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN); in msdc_init_hw()
1186 val = readl(&host->base->msdc_int); in msdc_init_hw()
1187 writel(val, &host->base->msdc_int); in msdc_init_hw()
1190 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten); in msdc_init_hw()
1193 writel(0, &host->base->msdc_iocon); in msdc_init_hw()
1195 if (host->r_smpl) in msdc_init_hw()
1196 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); in msdc_init_hw()
1198 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); in msdc_init_hw()
1200 writel(0x403c0046, &host->base->patch_bit0); in msdc_init_hw()
1201 writel(0xffff4089, &host->base->patch_bit1); in msdc_init_hw()
1203 if (host->dev_comp->stop_clk_fix) in msdc_init_hw()
1204 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M, in msdc_init_hw()
1207 if (host->dev_comp->busy_check) in msdc_init_hw()
1208 clrbits_le32(&host->base->patch_bit1, (1 << 7)); in msdc_init_hw()
1210 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1212 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1213 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M, in msdc_init_hw()
1216 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1217 setbits_le32(&host->base->sdc_adv_cfg0, in msdc_init_hw()
1220 clrsetbits_le32(&host->base->patch_bit2, in msdc_init_hw()
1223 clrsetbits_le32(&host->base->patch_bit2, in msdc_init_hw()
1229 clrbits_le32(&host->base->patch_bit2, in msdc_init_hw()
1231 clrbits_le32(&host->base->patch_bit2, in msdc_init_hw()
1235 if (host->dev_comp->data_tune) { in msdc_init_hw()
1238 clrsetbits_le32(&host->base->patch_bit0, in msdc_init_hw()
1240 host->latch_ck << in msdc_init_hw()
1248 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO); in msdc_init_hw()
1251 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE); in msdc_init_hw()
1254 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, in msdc_init_hw()
1257 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1258 clrbits_le32(&host->base->sdc_fifo_cfg, in msdc_init_hw()
1260 clrbits_le32(&host->base->sdc_fifo_cfg, in msdc_init_hw()
1264 host->def_tune_para.iocon = readl(&host->base->msdc_iocon); in msdc_init_hw()
1265 host->def_tune_para.pad_tune = readl(&host->base->pad_tune); in msdc_init_hw()
1270 clk_enable(&host->src_clk); in msdc_ungate_clock()
1271 clk_enable(&host->h_clk); in msdc_ungate_clock()
1279 struct mmc_config *cfg = &plat->cfg; in msdc_drv_probe()
1281 cfg->name = dev->name; in msdc_drv_probe()
1283 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev); in msdc_drv_probe()
1285 host->src_clk_freq = clk_get_rate(&host->src_clk); in msdc_drv_probe()
1287 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
1288 cfg->f_min = host->src_clk_freq / (4 * 255); in msdc_drv_probe()
1290 cfg->f_min = host->src_clk_freq / (4 * 4095); in msdc_drv_probe()
1291 cfg->f_max = host->src_clk_freq / 2; in msdc_drv_probe()
1293 cfg->b_max = 1024; in msdc_drv_probe()
1294 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; in msdc_drv_probe()
1296 host->mmc = &plat->mmc; in msdc_drv_probe()
1297 host->timeout_ns = 100000000; in msdc_drv_probe()
1298 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
1307 upriv->mmc = &plat->mmc; in msdc_drv_probe()
1316 struct mmc_config *cfg = &plat->cfg; in msdc_ofdata_to_platdata()
1319 host->base = (void *)dev_read_addr(dev); in msdc_ofdata_to_platdata()
1320 if (!host->base) in msdc_ofdata_to_platdata()
1321 return -EINVAL; in msdc_ofdata_to_platdata()
1327 ret = clk_get_by_name(dev, "source", &host->src_clk); in msdc_ofdata_to_platdata()
1331 ret = clk_get_by_name(dev, "hclk", &host->h_clk); in msdc_ofdata_to_platdata()
1336 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN); in msdc_ofdata_to_platdata()
1337 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN); in msdc_ofdata_to_platdata()
1340 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0); in msdc_ofdata_to_platdata()
1341 host->hs200_cmd_int_delay = in msdc_ofdata_to_platdata()
1343 host->hs200_write_int_delay = in msdc_ofdata_to_platdata()
1345 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); in msdc_ofdata_to_platdata()
1346 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0); in msdc_ofdata_to_platdata()
1347 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0); in msdc_ofdata_to_platdata()
1356 return mmc_bind(dev, &plat->mmc, &plat->cfg); in msdc_drv_bind()
1380 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },