Lines Matching +full:tx +full:- +full:ts +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0+
6 * Dante Su <dantesu@faraday-tech.com>
23 #include <dt-structs.h>
65 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_send_cmd()
66 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_send_cmd()
67 int ret = -ETIMEDOUT; in ftsdc010_send_cmd()
68 uint32_t ts, st; in ftsdc010_send_cmd() local
69 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx); in ftsdc010_send_cmd()
70 uint32_t arg = mmc_cmd->cmdarg; in ftsdc010_send_cmd()
71 uint32_t flags = mmc_cmd->resp_type; in ftsdc010_send_cmd()
75 if (chip->acmd) { in ftsdc010_send_cmd()
77 chip->acmd = 0; in ftsdc010_send_cmd()
87 ®s->clr); in ftsdc010_send_cmd()
88 writel(arg, ®s->argu); in ftsdc010_send_cmd()
89 writel(cmd, ®s->cmd); in ftsdc010_send_cmd()
92 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { in ftsdc010_send_cmd()
93 if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) { in ftsdc010_send_cmd()
94 writel(FTSDC010_STATUS_CMD_SEND, ®s->clr); in ftsdc010_send_cmd()
101 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { in ftsdc010_send_cmd()
102 st = readl(®s->status); in ftsdc010_send_cmd()
103 writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr); in ftsdc010_send_cmd()
109 mmc_cmd->response[0] = readl(®s->rsp3); in ftsdc010_send_cmd()
110 mmc_cmd->response[1] = readl(®s->rsp2); in ftsdc010_send_cmd()
111 mmc_cmd->response[2] = readl(®s->rsp1); in ftsdc010_send_cmd()
112 mmc_cmd->response[3] = readl(®s->rsp0); in ftsdc010_send_cmd()
114 mmc_cmd->response[0] = readl(®s->rsp0); in ftsdc010_send_cmd()
119 mmc_cmd->cmdidx, st); in ftsdc010_send_cmd()
125 mmc_cmd->cmdidx); in ftsdc010_send_cmd()
126 } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) { in ftsdc010_send_cmd()
127 chip->acmd = 1; in ftsdc010_send_cmd()
135 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_clkset()
136 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_clkset()
140 if (rate >= chip->sclk / (2 * (div + 1))) in ftsdc010_clkset()
143 chip->rate = chip->sclk / (2 * (div + 1)); in ftsdc010_clkset()
145 writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr); in ftsdc010_clkset()
148 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD); in ftsdc010_clkset()
150 if (chip->rate > 25000000) in ftsdc010_clkset()
151 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); in ftsdc010_clkset()
153 clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); in ftsdc010_clkset()
157 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) in ftsdc010_wait() argument
159 int ret = -ETIMEDOUT; in ftsdc010_wait()
161 while (timeout--) { in ftsdc010_wait()
162 st = readl(®s->status); in ftsdc010_wait()
163 if (!(st & mask)) in ftsdc010_wait()
165 writel(st & mask, ®s->clr); in ftsdc010_wait()
171 debug("ftsdc010: wait st(0x%x) timeout\n", mask); in ftsdc010_wait()
178 * u-boot mmc api
184 int ret = -EOPNOTSUPP; in ftsdc010_request()
186 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_request()
187 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_request()
189 if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) { in ftsdc010_request()
197 len = data->blocksize * data->blocks; in ftsdc010_request()
204 writel(dcr, ®s->dcr); in ftsdc010_request()
208 | FTSDC010_STATUS_FIFO_ORUN, ®s->clr); in ftsdc010_request()
211 writel(chip->rate, ®s->dtr); in ftsdc010_request()
214 writel(len, ®s->dlr); in ftsdc010_request()
217 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN; in ftsdc010_request()
218 if (data->flags & MMC_DATA_WRITE) in ftsdc010_request()
220 writel(dcr, ®s->dcr); in ftsdc010_request()
225 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx); in ftsdc010_request()
232 if (data->flags & MMC_DATA_WRITE) { in ftsdc010_request()
233 const uint8_t *buf = (const uint8_t *)data->src; in ftsdc010_request()
238 /* wait for tx ready */ in ftsdc010_request()
244 for (wlen = 0; wlen < len && wlen < chip->fifo; ) { in ftsdc010_request()
245 writel(*(uint32_t *)buf, ®s->dwr); in ftsdc010_request()
250 len -= wlen; in ftsdc010_request()
254 uint8_t *buf = (uint8_t *)data->dest; in ftsdc010_request()
265 for (rlen = 0; rlen < len && rlen < chip->fifo; ) { in ftsdc010_request()
266 *(uint32_t *)buf = readl(®s->dwr); in ftsdc010_request()
271 len -= rlen; in ftsdc010_request()
287 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_set_ios()
288 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_set_ios()
290 ftsdc010_clkset(mmc, mmc->clock); in ftsdc010_set_ios()
292 clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK); in ftsdc010_set_ios()
293 switch (mmc->bus_width) { in ftsdc010_set_ios()
295 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT); in ftsdc010_set_ios()
298 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT); in ftsdc010_set_ios()
301 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT); in ftsdc010_set_ios()
311 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_get_cd()
312 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_get_cd()
313 return !(readl(®s->status) & FTSDC010_STATUS_CARD_DETECT); in ftsdc010_get_cd()
319 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_get_wp()
320 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_get_wp()
321 if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) { in ftsdc010_get_wp()
323 chip->wprot = 1; in ftsdc010_get_wp()
331 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_init()
332 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_init()
333 uint32_t ts; in ftsdc010_init() local
335 chip->fifo = (readl(®s->feature) & 0xff) << 2; in ftsdc010_init()
338 writel(FTSDC010_CMD_SDC_RST, ®s->cmd); in ftsdc010_init()
339 for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) { in ftsdc010_init()
340 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) in ftsdc010_init()
344 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) { in ftsdc010_init()
346 return -EOPNOTSUPP; in ftsdc010_init()
353 writel(0, ®s->int_mask); in ftsdc010_init()
374 cfg->name = name; in ftsdc_setup_cfg()
375 cfg->f_min = min_clk; in ftsdc_setup_cfg()
376 cfg->f_max = max_clk; in ftsdc_setup_cfg()
377 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; in ftsdc_setup_cfg()
378 cfg->host_caps = caps; in ftsdc_setup_cfg()
380 cfg->host_caps |= MMC_MODE_8BIT; in ftsdc_setup_cfg()
381 cfg->host_caps &= ~MMC_MODE_4BIT; in ftsdc_setup_cfg()
383 cfg->host_caps |= MMC_MODE_4BIT; in ftsdc_setup_cfg()
384 cfg->host_caps &= ~MMC_MODE_8BIT; in ftsdc_setup_cfg()
386 cfg->part_type = PART_TYPE_DOS; in ftsdc_setup_cfg()
387 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; in ftsdc_setup_cfg()
394 struct ftsdc010_chip *chip = &priv->chip; in ftsdc010_mmc_ofdata_to_platdata()
395 chip->name = dev->name; in ftsdc010_mmc_ofdata_to_platdata()
396 chip->ioaddr = (void *)devfdt_get_addr(dev); in ftsdc010_mmc_ofdata_to_platdata()
397 chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in ftsdc010_mmc_ofdata_to_platdata()
398 "bus-width", 4); in ftsdc010_mmc_ofdata_to_platdata()
399 chip->priv = dev; in ftsdc010_mmc_ofdata_to_platdata()
400 priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in ftsdc010_mmc_ofdata_to_platdata()
401 "fifo-depth", 0); in ftsdc010_mmc_ofdata_to_platdata()
402 priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), in ftsdc010_mmc_ofdata_to_platdata()
403 "fifo-mode"); in ftsdc010_mmc_ofdata_to_platdata()
404 if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), in ftsdc010_mmc_ofdata_to_platdata()
405 "clock-freq-min-max", priv->minmax, 2)) { in ftsdc010_mmc_ofdata_to_platdata()
406 int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in ftsdc010_mmc_ofdata_to_platdata()
407 "max-frequency", -EINVAL); in ftsdc010_mmc_ofdata_to_platdata()
411 priv->minmax[0] = 400000; /* 400 kHz */ in ftsdc010_mmc_ofdata_to_platdata()
412 priv->minmax[1] = val; in ftsdc010_mmc_ofdata_to_platdata()
414 debug("%s: 'clock-freq-min-max' property was deprecated.\n", in ftsdc010_mmc_ofdata_to_platdata()
418 chip->sclk = priv->minmax[1]; in ftsdc010_mmc_ofdata_to_platdata()
419 chip->regs = chip->ioaddr; in ftsdc010_mmc_ofdata_to_platdata()
428 struct ftsdc010_chip *chip = &priv->chip; in ftsdc010_mmc_probe()
433 struct ftsdc010 *dtplat = &plat->dtplat; in ftsdc010_mmc_probe()
434 chip->name = dev->name; in ftsdc010_mmc_probe()
435 chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); in ftsdc010_mmc_probe()
436 chip->buswidth = dtplat->bus_width; in ftsdc010_mmc_probe()
437 chip->priv = dev; in ftsdc010_mmc_probe()
438 chip->dev_index = 1; in ftsdc010_mmc_probe()
439 memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); in ftsdc010_mmc_probe()
440 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); in ftsdc010_mmc_probe()
445 if (dev_read_bool(dev, "cap-mmc-highspeed") || \ in ftsdc010_mmc_probe()
446 dev_read_bool(dev, "cap-sd-highspeed")) in ftsdc010_mmc_probe()
447 chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; in ftsdc010_mmc_probe()
449 ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps, in ftsdc010_mmc_probe()
450 priv->minmax[1] , priv->minmax[0]); in ftsdc010_mmc_probe()
451 chip->mmc = &plat->mmc; in ftsdc010_mmc_probe()
452 chip->mmc->priv = &priv->chip; in ftsdc010_mmc_probe()
453 chip->mmc->dev = dev; in ftsdc010_mmc_probe()
454 upriv->mmc = chip->mmc; in ftsdc010_mmc_probe()
462 return mmc_bind(dev, &plat->mmc, &plat->cfg); in ftsdc010_mmc_bind()