1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
8  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
25 #include <asm-generic/gpio.h>
57 	uint    mixctrl;	/* For USDHC */
110  * @non_removable: 0: removable; 1: non-removable
162 		if (data->blocks > 1) {  in esdhc_xfertyp()
170 		if (data->flags & MMC_DATA_READ)  in esdhc_xfertyp()
174 	if (cmd->resp_type & MMC_RSP_CRC)  in esdhc_xfertyp()
176 	if (cmd->resp_type & MMC_RSP_OPCODE)  in esdhc_xfertyp()
178 	if (cmd->resp_type & MMC_RSP_136)  in esdhc_xfertyp()
180 	else if (cmd->resp_type & MMC_RSP_BUSY)  in esdhc_xfertyp()
182 	else if (cmd->resp_type & MMC_RSP_PRESENT)  in esdhc_xfertyp()
185 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)  in esdhc_xfertyp()
188 	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;  in esdhc_xfertyp()
198 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_pio_read_write()
206 	if (data->flags & MMC_DATA_READ) {  in esdhc_pio_read_write()
207 		blocks = data->blocks;  in esdhc_pio_read_write()
208 		buffer = data->dest;  in esdhc_pio_read_write()
211 			size = data->blocksize;  in esdhc_pio_read_write()
212 			irqstat = esdhc_read32(&regs->irqstat);  in esdhc_pio_read_write()
213 			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {  in esdhc_pio_read_write()
221 				irqstat = esdhc_read32(&regs->irqstat);  in esdhc_pio_read_write()
222 				databuf = in_le32(&regs->datport);  in esdhc_pio_read_write()
225 				size -= 4;  in esdhc_pio_read_write()
227 			blocks--;  in esdhc_pio_read_write()
230 		blocks = data->blocks;  in esdhc_pio_read_write()
231 		buffer = (char *)data->src;  in esdhc_pio_read_write()
234 			size = data->blocksize;  in esdhc_pio_read_write()
235 			irqstat = esdhc_read32(&regs->irqstat);  in esdhc_pio_read_write()
236 			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {  in esdhc_pio_read_write()
246 				size -= 4;  in esdhc_pio_read_write()
247 				irqstat = esdhc_read32(&regs->irqstat);  in esdhc_pio_read_write()
248 				out_le32(&regs->datport, databuf);  in esdhc_pio_read_write()
250 			blocks--;  in esdhc_pio_read_write()
260 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_setup_data()
267 	wml_value = data->blocksize/4;  in esdhc_setup_data()
269 	if (data->flags & MMC_DATA_READ) {  in esdhc_setup_data()
273 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);  in esdhc_setup_data()
277 		addr = virt_to_phys((void *)(data->dest));  in esdhc_setup_data()
281 			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));  in esdhc_setup_data()
283 		esdhc_write32(&regs->dsaddr, (u32)data->dest);  in esdhc_setup_data()
288 		flush_dcache_range((ulong)data->src,  in esdhc_setup_data()
289 				   (ulong)data->src+data->blocks  in esdhc_setup_data()
290 					 *data->blocksize);  in esdhc_setup_data()
294 		if (priv->wp_enable) {  in esdhc_setup_data()
295 			if ((esdhc_read32(&regs->prsstat) &  in esdhc_setup_data()
298 				return -ETIMEDOUT;  in esdhc_setup_data()
302 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,  in esdhc_setup_data()
307 		addr = virt_to_phys((void *)(data->src));  in esdhc_setup_data()
311 			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));  in esdhc_setup_data()
313 		esdhc_write32(&regs->dsaddr, (u32)data->src);  in esdhc_setup_data()
318 	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);  in esdhc_setup_data()
326 	 *		= (mmc->clock * 1/4) SD Clock cycles  in esdhc_setup_data()
328 	 * => (2^(timeout+13)) >= mmc->clock * 1/4  in esdhc_setup_data()
330 	 * => timeout + 13 >= log2(mmc->clock/4)  in esdhc_setup_data()
332 	 * => timeout + 13 = log2(mmc->clock/4) + 1  in esdhc_setup_data()
333 	 * => timeout + 13 = fls(mmc->clock/4)  in esdhc_setup_data()
340 	 * => timeout + 13 = fls(mmc->clock/2)  in esdhc_setup_data()
342 	timeout = fls(mmc->clock/2);  in esdhc_setup_data()
343 	timeout -= 13;  in esdhc_setup_data()
359 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);  in esdhc_setup_data()
370 				data->blocks*data->blocksize);  in check_and_invalidate_dcache_range()
375 	addr = virt_to_phys((void *)(data->dest));  in check_and_invalidate_dcache_range()
381 	start = (unsigned)data->dest;  in check_and_invalidate_dcache_range()
389  * Swaps 32-bit words to little-endian byte order.
393 	int i, size = data->blocksize >> 2;  in sd_swap_dma_buff()
394 	u32 *buffer = (u32 *)data->dest;  in sd_swap_dma_buff()
397 	while (data->blocks--) {  in sd_swap_dma_buff()
417 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_send_cmd_common()
421 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)  in esdhc_send_cmd_common()
425 	esdhc_write32(&regs->irqstat, -1);  in esdhc_send_cmd_common()
430 	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||  in esdhc_send_cmd_common()
431 			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))  in esdhc_send_cmd_common()
434 	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)  in esdhc_send_cmd_common()
450 		if (data->flags & MMC_DATA_READ)  in esdhc_send_cmd_common()
458 	esdhc_write32(&regs->irqsigen, 0);  in esdhc_send_cmd_common()
461 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);  in esdhc_send_cmd_common()
463 	esdhc_write32(&regs->mixctrl,  in esdhc_send_cmd_common()
464 	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)  in esdhc_send_cmd_common()
465 			| (mmc->ddr_mode ? XFERTYP_DDREN : 0));  in esdhc_send_cmd_common()
466 	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);  in esdhc_send_cmd_common()
468 	esdhc_write32(&regs->xfertyp, xfertyp);  in esdhc_send_cmd_common()
471 	if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||  in esdhc_send_cmd_common()
472 	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))  in esdhc_send_cmd_common()
477 	while (!(esdhc_read32(&regs->irqstat) & flags)) {  in esdhc_send_cmd_common()
479 			err = -ETIMEDOUT;  in esdhc_send_cmd_common()
484 	irqstat = esdhc_read32(&regs->irqstat);  in esdhc_send_cmd_common()
487 		err = -ECOMM;  in esdhc_send_cmd_common()
492 		err = -ETIMEDOUT;  in esdhc_send_cmd_common()
497 	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {  in esdhc_send_cmd_common()
498 		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);  in esdhc_send_cmd_common()
501 		/* Sleep for 5 ms - max time for card to switch to 1.8V */  in esdhc_send_cmd_common()
506 	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {  in esdhc_send_cmd_common()
510 		while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &  in esdhc_send_cmd_common()
513 			timeout--;  in esdhc_send_cmd_common()
518 			err = -ETIMEDOUT;  in esdhc_send_cmd_common()
524 	if (cmd->resp_type & MMC_RSP_136) {  in esdhc_send_cmd_common()
527 		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);  in esdhc_send_cmd_common()
528 		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);  in esdhc_send_cmd_common()
529 		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);  in esdhc_send_cmd_common()
530 		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);  in esdhc_send_cmd_common()
531 		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);  in esdhc_send_cmd_common()
532 		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);  in esdhc_send_cmd_common()
533 		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);  in esdhc_send_cmd_common()
534 		cmd->response[3] = (cmdrsp0 << 8);  in esdhc_send_cmd_common()
536 		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);  in esdhc_send_cmd_common()
544 		if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||  in esdhc_send_cmd_common()
545 		    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {  in esdhc_send_cmd_common()
550 			irqstat = esdhc_read32(&regs->irqstat);  in esdhc_send_cmd_common()
553 				err = -ETIMEDOUT;  in esdhc_send_cmd_common()
558 				err = -ECOMM;  in esdhc_send_cmd_common()
565 		 * cache-fill during the DMA operations such as the  in esdhc_send_cmd_common()
566 		 * speculative pre-fetching etc.  in esdhc_send_cmd_common()
568 		if (data->flags & MMC_DATA_READ) {  in esdhc_send_cmd_common()
580 		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |  in esdhc_send_cmd_common()
582 		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)  in esdhc_send_cmd_common()
586 			esdhc_write32(&regs->sysctl,  in esdhc_send_cmd_common()
587 				      esdhc_read32(&regs->sysctl) |  in esdhc_send_cmd_common()
589 			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))  in esdhc_send_cmd_common()
594 		if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)  in esdhc_send_cmd_common()
598 	esdhc_write32(&regs->irqstat, -1);  in esdhc_send_cmd_common()
605 	struct fsl_esdhc *regs = priv->esdhc_regs;  in set_sysctl()
617 	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;  in set_sysctl()
618 	int sdhc_clk = priv->sdhc_clk;  in set_sysctl()
621 	if (clock < mmc->cfg->f_min)  in set_sysctl()
622 		clock = mmc->cfg->f_min;  in set_sysctl()
631 	div -= 1;  in set_sysctl()
636 	esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);  in set_sysctl()
638 	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);  in set_sysctl()
641 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);  in set_sysctl()
646 	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);  in set_sysctl()
648 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);  in set_sysctl()
651 	priv->clock = clock;  in set_sysctl()
657 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_clock_control()
661 	value = esdhc_read32(&regs->sysctl);  in esdhc_clock_control()
668 	esdhc_write32(&regs->sysctl, value);  in esdhc_clock_control()
672 	while (!(esdhc_read32(&regs->prsstat) & value)) {  in esdhc_clock_control()
677 		time_out--;  in esdhc_clock_control()
689 	switch (priv->mode) {  in esdhc_change_pinstate()
705 		printf("%s %d error\n", __func__, priv->mode);  in esdhc_change_pinstate()
712 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);  in esdhc_reset_tuning()
713 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_reset_tuning()
715 	if (priv->flags & ESDHC_FLAG_USDHC) {  in esdhc_reset_tuning()
716 		if (priv->flags & ESDHC_FLAG_STD_TUNING) {  in esdhc_reset_tuning()
717 			esdhc_clrbits32(&regs->autoc12err,  in esdhc_reset_tuning()
726 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);  in esdhc_set_strobe_dll()
727 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_set_strobe_dll()
730 	if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {  in esdhc_set_strobe_dll()
731 		writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);  in esdhc_set_strobe_dll()
735 		 * for the uSDHC loopback read clock  in esdhc_set_strobe_dll()
738 			(priv->strobe_dll_delay_target <<  in esdhc_set_strobe_dll()
740 		writel(val, &regs->strobe_dllctrl);  in esdhc_set_strobe_dll()
743 		val = readl(&regs->strobe_dllstat);  in esdhc_set_strobe_dll()
753 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);  in esdhc_set_timing()
754 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_set_timing()
757 	mixctrl = readl(&regs->mixctrl);  in esdhc_set_timing()
760 	switch (mmc->selected_mode) {  in esdhc_set_timing()
764 		writel(mixctrl, &regs->mixctrl);  in esdhc_set_timing()
768 		writel(mixctrl, &regs->mixctrl);  in esdhc_set_timing()
779 		writel(mixctrl, &regs->mixctrl);  in esdhc_set_timing()
784 		writel(mixctrl, &regs->mixctrl);  in esdhc_set_timing()
787 		printf("Not supported %d\n", mmc->selected_mode);  in esdhc_set_timing()
788 		return -EINVAL;  in esdhc_set_timing()
791 	priv->mode = mmc->selected_mode;  in esdhc_set_timing()
793 	return esdhc_change_pinstate(mmc->dev);  in esdhc_set_timing()
798 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);  in esdhc_set_voltage()
799 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_set_voltage()
802 	priv->signal_voltage = mmc->signal_voltage;  in esdhc_set_voltage()
803 	switch (mmc->signal_voltage) {  in esdhc_set_voltage()
805 		if (priv->vs18_enable)  in esdhc_set_voltage()
806 			return -EIO;  in esdhc_set_voltage()
808 		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {  in esdhc_set_voltage()
809 			ret = regulator_set_value(priv->vqmmc_dev, 3300000);  in esdhc_set_voltage()
812 				return -EIO;  in esdhc_set_voltage()
819 		esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);  in esdhc_set_voltage()
820 		if (!(esdhc_read32(&regs->vendorspec) &  in esdhc_set_voltage()
824 		return -EAGAIN;  in esdhc_set_voltage()
827 		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {  in esdhc_set_voltage()
828 			ret = regulator_set_value(priv->vqmmc_dev, 1800000);  in esdhc_set_voltage()
831 				return -EIO;  in esdhc_set_voltage()
835 		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);  in esdhc_set_voltage()
836 		if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)  in esdhc_set_voltage()
839 		return -EAGAIN;  in esdhc_set_voltage()
841 		return -ENOTSUPP;  in esdhc_set_voltage()
855 	dm_mmc_send_cmd(mmc->dev, &cmd, NULL);  in esdhc_stop_tuning()
862 	struct fsl_esdhc *regs = priv->esdhc_regs;  in fsl_esdhc_execute_tuning()
863 	struct mmc *mmc = &plat->mmc;  in fsl_esdhc_execute_tuning()
864 	u32 irqstaten = readl(&regs->irqstaten);  in fsl_esdhc_execute_tuning()
865 	u32 irqsigen = readl(&regs->irqsigen);  in fsl_esdhc_execute_tuning()
866 	int i, ret = -ETIMEDOUT;  in fsl_esdhc_execute_tuning()
870 	if (mmc->clock <= 52000000)  in fsl_esdhc_execute_tuning()
874 	if (priv->flags & ESDHC_FLAG_STD_TUNING) {  in fsl_esdhc_execute_tuning()
875 		val = readl(&regs->autoc12err);  in fsl_esdhc_execute_tuning()
876 		mixctrl = readl(&regs->mixctrl);  in fsl_esdhc_execute_tuning()
883 		writel(val, &regs->autoc12err);  in fsl_esdhc_execute_tuning()
884 		writel(mixctrl, &regs->mixctrl);  in fsl_esdhc_execute_tuning()
888 	mixctrl = readl(&regs->mixctrl);  in fsl_esdhc_execute_tuning()
890 	writel(mixctrl, &regs->mixctrl);  in fsl_esdhc_execute_tuning()
892 	writel(IRQSTATEN_BRR, &regs->irqstaten);  in fsl_esdhc_execute_tuning()
893 	writel(IRQSTATEN_BRR, &regs->irqsigen);  in fsl_esdhc_execute_tuning()
903 			if (mmc->bus_width == 8)  in fsl_esdhc_execute_tuning()
904 				writel(0x7080, &regs->blkattr);  in fsl_esdhc_execute_tuning()
905 			else if (mmc->bus_width == 4)  in fsl_esdhc_execute_tuning()
906 				writel(0x7040, &regs->blkattr);  in fsl_esdhc_execute_tuning()
908 			writel(0x7040, &regs->blkattr);  in fsl_esdhc_execute_tuning()
912 		val = readl(&regs->mixctrl);  in fsl_esdhc_execute_tuning()
914 		writel(val, &regs->mixctrl);  in fsl_esdhc_execute_tuning()
919 		ctrl = readl(&regs->autoc12err);  in fsl_esdhc_execute_tuning()
937 	writel(irqstaten, &regs->irqstaten);  in fsl_esdhc_execute_tuning()
938 	writel(irqsigen, &regs->irqsigen);  in fsl_esdhc_execute_tuning()
948 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_set_ios_common()
954 	esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);  in esdhc_set_ios_common()
958 	if (priv->clock != mmc->clock)  in esdhc_set_ios_common()
959 		set_sysctl(priv, mmc, mmc->clock);  in esdhc_set_ios_common()
962 	if (mmc->clk_disable) {  in esdhc_set_ios_common()
964 		esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);  in esdhc_set_ios_common()
966 		esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);  in esdhc_set_ios_common()
970 		esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |  in esdhc_set_ios_common()
973 		esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);  in esdhc_set_ios_common()
977 	if (priv->mode != mmc->selected_mode) {  in esdhc_set_ios_common()
985 	if (priv->signal_voltage != mmc->signal_voltage) {  in esdhc_set_ios_common()
995 	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);  in esdhc_set_ios_common()
997 	if (mmc->bus_width == 4)  in esdhc_set_ios_common()
998 		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);  in esdhc_set_ios_common()
999 	else if (mmc->bus_width == 8)  in esdhc_set_ios_common()
1000 		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);  in esdhc_set_ios_common()
1007 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_init_common()
1011 	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);  in esdhc_init_common()
1015 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {  in esdhc_init_common()
1017 			return -ETIMEDOUT;  in esdhc_init_common()
1022 	esdhc_write32(&regs->mmcboot, 0x0);  in esdhc_init_common()
1024 	esdhc_write32(&regs->mixctrl, 0x0);  in esdhc_init_common()
1025 	esdhc_write32(&regs->clktunectrlstatus, 0x0);  in esdhc_init_common()
1028 	if (priv->vs18_enable)  in esdhc_init_common()
1029 		esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |  in esdhc_init_common()
1032 		esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);  in esdhc_init_common()
1035 	esdhc_write32(&regs->dllctrl, 0x0);  in esdhc_init_common()
1040 	esdhc_write32(&regs->scr, 0x00000040);  in esdhc_init_common()
1044 	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);  in esdhc_init_common()
1046 	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);  in esdhc_init_common()
1053 	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);  in esdhc_init_common()
1056 	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);  in esdhc_init_common()
1059 	esdhc_write32(&regs->proctl, PROCTL_INIT);  in esdhc_init_common()
1063 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);  in esdhc_init_common()
1070 	struct fsl_esdhc *regs = priv->esdhc_regs;  in esdhc_getcd_common()
1079 	if (priv->non_removable)  in esdhc_getcd_common()
1082 	if (dm_gpio_is_valid(&priv->cd_gpio))  in esdhc_getcd_common()
1083 		return dm_gpio_get_value(&priv->cd_gpio);  in esdhc_getcd_common()
1087 	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)  in esdhc_getcd_common()
1098 	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);  in esdhc_reset()
1102 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {  in esdhc_reset()
1105 			return -ETIMEDOUT;  in esdhc_reset()
1115 	struct fsl_esdhc_priv *priv = mmc->priv;  in esdhc_getcd()
1122 	struct fsl_esdhc_priv *priv = mmc->priv;  in esdhc_init()
1130 	struct fsl_esdhc_priv *priv = mmc->priv;  in esdhc_send_cmd()
1137 	struct fsl_esdhc_priv *priv = mmc->priv;  in esdhc_set_ios()
1159 		return -EINVAL;  in fsl_esdhc_init()
1161 	regs = priv->esdhc_regs;  in fsl_esdhc_init()
1170 	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);  in fsl_esdhc_init()
1174 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN  in fsl_esdhc_init()
1177 	esdhc_write32(&regs->mixctrl, 0);  in fsl_esdhc_init()
1178 	esdhc_write32(&regs->autoc12err, 0);  in fsl_esdhc_init()
1179 	esdhc_write32(&regs->clktunectrlstatus, 0);  in fsl_esdhc_init()
1181 	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |  in fsl_esdhc_init()
1185 	if (priv->vs18_enable)  in fsl_esdhc_init()
1186 		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);  in fsl_esdhc_init()
1188 	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);  in fsl_esdhc_init()
1189 	cfg = &plat->cfg;  in fsl_esdhc_init()
1195 	caps = esdhc_read32(&regs->hostcapblt);  in fsl_esdhc_init()
1223 	cfg->name = "FSL_SDHC";  in fsl_esdhc_init()
1225 	cfg->ops = &esdhc_ops;  in fsl_esdhc_init()
1228 	cfg->voltages = CONFIG_SYS_SD_VOLTAGE;  in fsl_esdhc_init()
1230 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;  in fsl_esdhc_init()
1232 	if ((cfg->voltages & voltage_caps) == 0) {  in fsl_esdhc_init()
1234 		return -1;  in fsl_esdhc_init()
1237 	if (priv->bus_width == 8)  in fsl_esdhc_init()
1238 		cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;  in fsl_esdhc_init()
1239 	else if (priv->bus_width == 4)  in fsl_esdhc_init()
1240 		cfg->host_caps = MMC_MODE_4BIT;  in fsl_esdhc_init()
1242 	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;  in fsl_esdhc_init()
1244 	cfg->host_caps |= MMC_MODE_DDR_52MHz;  in fsl_esdhc_init()
1247 	if (priv->bus_width > 0) {  in fsl_esdhc_init()
1248 		if (priv->bus_width < 8)  in fsl_esdhc_init()
1249 			cfg->host_caps &= ~MMC_MODE_8BIT;  in fsl_esdhc_init()
1250 		if (priv->bus_width < 4)  in fsl_esdhc_init()
1251 			cfg->host_caps &= ~MMC_MODE_4BIT;  in fsl_esdhc_init()
1255 		cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;  in fsl_esdhc_init()
1259 		cfg->host_caps &= ~MMC_MODE_8BIT;  in fsl_esdhc_init()
1262 	cfg->host_caps |= priv->caps;  in fsl_esdhc_init()
1264 	cfg->f_min = 400000;  in fsl_esdhc_init()
1265 	cfg->f_max = min(priv->sdhc_clk, (u32)200000000);  in fsl_esdhc_init()
1267 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;  in fsl_esdhc_init()
1269 	writel(0, &regs->dllctrl);  in fsl_esdhc_init()
1270 	if (priv->flags & ESDHC_FLAG_USDHC) {  in fsl_esdhc_init()
1271 		if (priv->flags & ESDHC_FLAG_STD_TUNING) {  in fsl_esdhc_init()
1272 			u32 val = readl(&regs->tuning_ctrl);  in fsl_esdhc_init()
1276 			val |= priv->tuning_start_tap;  in fsl_esdhc_init()
1278 			val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;  in fsl_esdhc_init()
1279 			writel(val, &regs->tuning_ctrl);  in fsl_esdhc_init()
1291 		return -EINVAL;  in fsl_esdhc_cfg_to_priv()
1293 	priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);  in fsl_esdhc_cfg_to_priv()
1294 	priv->bus_width = cfg->max_bus_width;  in fsl_esdhc_cfg_to_priv()
1295 	priv->sdhc_clk = cfg->sdhc_clk;  in fsl_esdhc_cfg_to_priv()
1296 	priv->wp_enable  = cfg->wp_enable;  in fsl_esdhc_cfg_to_priv()
1297 	priv->vs18_enable  = cfg->vs18_enable;  in fsl_esdhc_cfg_to_priv()
1310 		return -EINVAL;  in fsl_esdhc_initialize()
1314 		return -ENOMEM;  in fsl_esdhc_initialize()
1318 		return -ENOMEM;  in fsl_esdhc_initialize()
1337 	mmc = mmc_create(&plat->cfg, priv);  in fsl_esdhc_initialize()
1339 		return -EIO;  in fsl_esdhc_initialize()
1341 	priv->mmc = mmc;  in fsl_esdhc_initialize()
1351 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;  in fsl_esdhc_mmc_init()
1352 	cfg->sdhc_clk = gd->arch.sdhc_clk;  in fsl_esdhc_mmc_init()
1364 	gd->arch.sdhc_adapter = card_id;  in mmc_adapter_card_type_ident()
1417 	do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",  in fdt_fixup_esdhc()
1418 			       gd->arch.sdhc_clk, 1);  in fdt_fixup_esdhc()
1420 	do_fixup_by_compat_u32(blob, compat, "clock-frequency",  in fdt_fixup_esdhc()
1421 			       gd->arch.sdhc_clk, 1);  in fdt_fixup_esdhc()
1424 	do_fixup_by_compat_u32(blob, compat, "adapter-type",  in fdt_fixup_esdhc()
1425 			       (u32)(gd->arch.sdhc_adapter), 1);  in fdt_fixup_esdhc()
1441 	const void *fdt = gd->fdt_blob;  in fsl_esdhc_probe()
1455 		return -EINVAL;  in fsl_esdhc_probe()
1457 	priv->esdhc_regs = (struct fsl_esdhc *)addr;  in fsl_esdhc_probe()
1458 	priv->dev = dev;  in fsl_esdhc_probe()
1459 	priv->mode = -1;  in fsl_esdhc_probe()
1461 		priv->flags = data->flags;  in fsl_esdhc_probe()
1462 		priv->caps = data->caps;  in fsl_esdhc_probe()
1465 	val = dev_read_u32_default(dev, "bus-width", -1);  in fsl_esdhc_probe()
1467 		priv->bus_width = 8;  in fsl_esdhc_probe()
1469 		priv->bus_width = 4;  in fsl_esdhc_probe()
1471 		priv->bus_width = 1;  in fsl_esdhc_probe()
1473 	val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);  in fsl_esdhc_probe()
1474 	priv->tuning_step = val;  in fsl_esdhc_probe()
1475 	val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",  in fsl_esdhc_probe()
1477 	priv->tuning_start_tap = val;  in fsl_esdhc_probe()
1478 	val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",  in fsl_esdhc_probe()
1480 	priv->strobe_dll_delay_target = val;  in fsl_esdhc_probe()
1482 	if (dev_read_bool(dev, "non-removable")) {  in fsl_esdhc_probe()
1483 		priv->non_removable = 1;  in fsl_esdhc_probe()
1485 		priv->non_removable = 0;  in fsl_esdhc_probe()
1487 		gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,  in fsl_esdhc_probe()
1492 	priv->wp_enable = 1;  in fsl_esdhc_probe()
1495 	ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,  in fsl_esdhc_probe()
1498 		priv->wp_enable = 0;  in fsl_esdhc_probe()
1501 	priv->vs18_enable = 0;  in fsl_esdhc_probe()
1508 	ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);  in fsl_esdhc_probe()
1510 		dev_dbg(dev, "no vqmmc-supply\n");  in fsl_esdhc_probe()
1514 			dev_err(dev, "fail to enable vqmmc-supply\n");  in fsl_esdhc_probe()
1519 			priv->vs18_enable = 1;  in fsl_esdhc_probe()
1523 	if (fdt_get_property(fdt, node, "no-1-8-v", NULL))  in fsl_esdhc_probe()
1524 		priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);  in fsl_esdhc_probe()
1546 	init_clk_usdhc(dev->seq);  in fsl_esdhc_probe()
1550 		ret = clk_get_by_name(dev, "per", &priv->per_clk);  in fsl_esdhc_probe()
1555 		ret = clk_enable(&priv->per_clk);  in fsl_esdhc_probe()
1561 		priv->sdhc_clk = clk_get_rate(&priv->per_clk);  in fsl_esdhc_probe()
1563 		priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);  in fsl_esdhc_probe()
1564 		if (priv->sdhc_clk <= 0) {  in fsl_esdhc_probe()
1565 			dev_err(dev, "Unable to get clk for %s\n", dev->name);  in fsl_esdhc_probe()
1566 			return -EINVAL;  in fsl_esdhc_probe()
1576 	mmc = &plat->mmc;  in fsl_esdhc_probe()
1577 	mmc->cfg = &plat->cfg;  in fsl_esdhc_probe()
1578 	mmc->dev = dev;  in fsl_esdhc_probe()
1579 	upriv->mmc = mmc;  in fsl_esdhc_probe()
1598 	return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);  in fsl_esdhc_send_cmd()
1606 	return esdhc_set_ios_common(priv, &plat->mmc);  in fsl_esdhc_set_ios()
1628 	{ .compatible = "fsl,imx53-esdhc", },
1629 	{ .compatible = "fsl,imx6ul-usdhc", },
1630 	{ .compatible = "fsl,imx6sx-usdhc", },
1631 	{ .compatible = "fsl,imx6sl-usdhc", },
1632 	{ .compatible = "fsl,imx6q-usdhc", },
1633 	{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1634 	{ .compatible = "fsl,imx7ulp-usdhc", },
1644 	return mmc_bind(dev, &plat->mmc, &plat->cfg);  in fsl_esdhc_bind()
1649 	.name	= "fsl-esdhc-mmc",