drivers/mmc/dw_mmc.c

19 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)  in dwmci_wait_reset()  argument
24 	dwmci_writel(host, DWMCI_CTRL, value);  in dwmci_wait_reset()
27 		ctrl = dwmci_readl(host, DWMCI_CTRL);  in dwmci_wait_reset()
45 static void dwmci_prepare_data(struct dwmci_host *host,  in dwmci_prepare_data()  argument
57 	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);  in dwmci_prepare_data()
60 	dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);  in dwmci_prepare_data()
63 	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);  in dwmci_prepare_data()
87 	ctrl = dwmci_readl(host, DWMCI_CTRL);  in dwmci_prepare_data()
89 	dwmci_writel(host, DWMCI_CTRL, ctrl);  in dwmci_prepare_data()
91 	ctrl = dwmci_readl(host, DWMCI_BMOD);  in dwmci_prepare_data()
93 	dwmci_writel(host, DWMCI_BMOD, ctrl);  in dwmci_prepare_data()
95 	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);  in dwmci_prepare_data()
96 	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);  in dwmci_prepare_data()
99 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)  in dwmci_fifo_ready()  argument
103 	*len = dwmci_readl(host, DWMCI_STATUS);  in dwmci_fifo_ready()
106 		*len = dwmci_readl(host, DWMCI_STATUS);  in dwmci_fifo_ready()
117 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)  in dwmci_data_transfer()  argument
124 	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>  in dwmci_data_transfer()
134 		mask = dwmci_readl(host, DWMCI_RINTSTS);  in dwmci_data_transfer()
142 		if (host->fifo_mode && size) {  in dwmci_data_transfer()
147 					ret = dwmci_fifo_ready(host,  in dwmci_data_transfer()
158 						dwmci_readl(host, DWMCI_DATA);  in dwmci_data_transfer()
161 				dwmci_writel(host, DWMCI_RINTSTS,  in dwmci_data_transfer()
166 					ret = dwmci_fifo_ready(host,  in dwmci_data_transfer()
177 						dwmci_writel(host, DWMCI_DATA,  in dwmci_data_transfer()
181 				dwmci_writel(host, DWMCI_RINTSTS,  in dwmci_data_transfer()
201 	dwmci_writel(host, DWMCI_RINTSTS, mask);  in dwmci_data_transfer()
206 static int dwmci_set_transfer_mode(struct dwmci_host *host,  in dwmci_set_transfer_mode()  argument
228 	struct dwmci_host *host = mmc->priv;  local
238 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
245 	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
248 		if (host->fifo_mode) {
249 			dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
250 			dwmci_writel(host, DWMCI_BYTCNT,
252 			dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
263 			dwmci_prepare_data(host, data, cur_idmac,
268 	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
271 		flags = dwmci_set_transfer_mode(host, data);
294 	dwmci_writel(host, DWMCI_CMD, flags);
297 		mask = dwmci_readl(host, DWMCI_RINTSTS);
300 				dwmci_writel(host, DWMCI_RINTSTS, mask);
333 			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
334 			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
335 			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
336 			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
338 			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
343 		ret = dwmci_data_transfer(host, data);
346 		if (!host->fifo_mode) {
351 			ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
357 			dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
359 			ctrl = dwmci_readl(host, DWMCI_CTRL);
361 			dwmci_writel(host, DWMCI_CTRL, ctrl);
371 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)  argument
377 	if ((freq == host->clock) || (freq == 0))
380 	 * If host->get_mmc_clk isn't defined,
381 	 * then assume that host->bus_hz is source clock value.
382 	 * host->bus_hz should be set by user.
384 	if (host->get_mmc_clk)
385 		sclk = host->get_mmc_clk(host, freq);
386 	else if (host->bus_hz)
387 		sclk = host->bus_hz;
398 	dwmci_writel(host, DWMCI_CLKENA, 0);
399 	dwmci_writel(host, DWMCI_CLKSRC, 0);
401 	dwmci_writel(host, DWMCI_CLKDIV, div);
402 	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
406 		status = dwmci_readl(host, DWMCI_CMD);
413 	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
416 	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
421 		status = dwmci_readl(host, DWMCI_CMD);
428 	host->clock = freq;
441 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;  local
446 	dwmci_setup_bus(host, mmc->clock);
459 	dwmci_writel(host, DWMCI_CTYPE, ctype);
461 	regs = dwmci_readl(host, DWMCI_UHS_REG);
467 	dwmci_writel(host, DWMCI_UHS_REG, regs);
469 	if (host->clksel)
470 		host->clksel(host);
477 	struct dwmci_host *host = mmc->priv;  local
479 	if (host->board_init)
480 		host->board_init(host);
482 	dwmci_writel(host, DWMCI_PWREN, 1);
484 	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
490 	dwmci_setup_bus(host, mmc->cfg->f_min);
492 	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
493 	dwmci_writel(host, DWMCI_INTMASK, 0);
495 	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
497 	dwmci_writel(host, DWMCI_IDINTEN, 0);
498 	dwmci_writel(host, DWMCI_BMOD, 1);
500 	if (!host->fifoth_val) {
503 		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
505 		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
508 	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
510 	dwmci_writel(host, DWMCI_CLKENA, 0);
511 	dwmci_writel(host, DWMCI_CLKSRC, 0);
513 	if (!host->fifo_mode)
514 		dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
540 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,  argument
543 	cfg->name = host->name;
552 	cfg->host_caps = host->caps;
554 	if (host->buswidth == 8) {
572 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)  argument
574 	dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
576 	host->mmc = mmc_create(&host->cfg, host);
577 	if (host->mmc == NULL)