1 // SPDX-License-Identifier: GPL-2.0+
7  * Based on Linux 4.14.y i2c-xiic.c
8  * Copyright (c) 2002-2007 Xilinx Inc.
9  * Copyright (c) 2009-2010 Intel Corporation
33 #define XIIC_DTR_REG_OFFSET  (0x08+XIIC_REG_OFFSET)	/* Data Tx Register   */
36 #define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)	/* Tx FIFO Occupancy  */
37 #define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)	/* Rx FIFO Occupancy  */
39 #define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)	/* Rx FIFO Depth reg  */
44 #define XIIC_CR_TX_FIFO_RESET_MASK        0x02	/* Transmit FIFO reset=1  */
46 #define XIIC_CR_DIR_IS_TX_MASK            0x08	/* Dir of tx. Txing=1     */
47 #define XIIC_CR_NO_ACK_MASK               0x10	/* Tx Ack. NO ack = 1     */
55 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08	/* 1=Dir: mstr <-- slave  */
56 #define XIIC_SR_TX_FIFO_FULL_MASK         0x10	/* 1 = Tx FIFO full       */
57 #define XIIC_SR_RX_FIFO_FULL_MASK         0x20	/* 1 = Rx FIFO full       */
58 #define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40	/* 1 = Rx FIFO empty      */
59 #define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80	/* 1 = Tx FIFO empty      */
63 #define XIIC_INTR_TX_ERROR_MASK           0x02	/* 1=Tx error/msg complete */
64 #define XIIC_INTR_TX_EMPTY_MASK           0x04	/* 1 = Tx FIFO/reg empty  */
65 #define XIIC_INTR_RX_FULL_MASK            0x08	/* 1=Rx FIFO/reg=OCY level */
69 #define XIIC_INTR_TX_HALF_MASK            0x80	/* 1 = TX FIFO half empty */
71 /* The following constants specify the depth of the FIFOs */
72 #define IIC_RX_FIFO_DEPTH         16	/* Rx fifo capacity               */
73 #define IIC_TX_FIFO_DEPTH         16	/* Tx fifo capacity               */
76  * Tx Fifo upper bit masks.
101 	u32 isr = readl(priv->base + XIIC_IISR_OFFSET);  in xiic_irq_clr()
103 	writel(isr & mask, priv->base + XIIC_IISR_OFFSET);  in xiic_irq_clr()
113 	while (pos < msg->len) {  in xiic_read_rx()
114 		ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,  in xiic_read_rx()
120 		bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1;  in xiic_read_rx()
122 		if (bytes_in_fifo > msg->len)  in xiic_read_rx()
123 			bytes_in_fifo = msg->len;  in xiic_read_rx()
126 			msg->buf[pos++] = readb(priv->base +  in xiic_read_rx()
136 	/* return the actual space left in the FIFO */  in xiic_tx_fifo_space()
137 	return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1;  in xiic_tx_fifo_space()
144 	int len = msg->len;  in xiic_fill_tx_fifo()
149 	while (len--) {  in xiic_fill_tx_fifo()
150 		u16 data = msg->buf[pos++];  in xiic_fill_tx_fifo()
153 			/* last message in transfer -> STOP */  in xiic_fill_tx_fifo()
156 		writew(data, priv->base + XIIC_DTR_REG_OFFSET);  in xiic_fill_tx_fifo()
172 			/* no data and last message -> add STOP */  in xilinx_xiic_set_addr()
175 		writew(data, priv->base + XIIC_DTR_REG_OFFSET);  in xilinx_xiic_set_addr()
194 	rx_watermark = msg->len;  in xilinx_xiic_read_common()
198 	writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET);  in xilinx_xiic_read_common()
200 	xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);  in xilinx_xiic_read_common()
204 	writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0),  in xilinx_xiic_read_common()
205 	       priv->base + XIIC_DTR_REG_OFFSET);  in xilinx_xiic_read_common()
220 	xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);  in xilinx_xiic_write_common()
223 	ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,  in xilinx_xiic_write_common()
228 	/* Clear any pending Tx empty, Tx Error and then enable them. */  in xilinx_xiic_write_common()
239 	for (sr = readb(priv->base + XIIC_SR_REG_OFFSET);  in xiic_clear_rx_fifo()
241 		sr = readb(priv->base + XIIC_SR_REG_OFFSET))  in xiic_clear_rx_fifo()
242 		readb(priv->base + XIIC_DRR_REG_OFFSET);  in xiic_clear_rx_fifo()
247 	writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET);  in xiic_reinit()
249 	/* Set receive Fifo depth to maximum (zero based). */  in xiic_reinit()
250 	writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET);  in xiic_reinit()
252 	/* Reset Tx Fifo. */  in xiic_reinit()
253 	writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);  in xiic_reinit()
255 	/* Enable IIC Device, remove Tx Fifo reset & disable general call. */  in xiic_reinit()
256 	writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET);  in xiic_reinit()
258 	/* make sure RX fifo is empty */  in xiic_reinit()
262 	writel(0, priv->base + XIIC_DGIER_OFFSET);  in xiic_reinit()
271 	for (; nmsgs > 0; nmsgs--, msg++) {  in xilinx_xiic_xfer()
272 		if (msg->flags & I2C_M_RD)  in xilinx_xiic_xfer()
278 			return -EREMOTEIO;  in xilinx_xiic_xfer()
293 	ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,  in xilinx_xiic_probe_chip()
298 	reg = readl(priv->base + XIIC_IISR_OFFSET);  in xilinx_xiic_probe_chip()
300 		return -ENODEV;  in xilinx_xiic_probe_chip()
314 	priv->base = dev_read_addr_ptr(dev);  in xilinx_xiic_probe()
316 	writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);  in xilinx_xiic_probe()
329 	{ .compatible = "xlnx,xps-iic-2.00.a" },