Lines Matching +full:send +full:- +full:not +full:- +full:empty
1 // SPDX-License-Identifier: GPL-2.0+
4 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
16 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
65 * i2c_reset: - reset the host controller
73 icr_mode = readl(&base->icr) & ICR_MODE_MASK; in i2c_reset()
74 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
75 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ in i2c_reset()
77 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
81 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ in i2c_reset()
83 writel(I2C_ICR_INIT | icr_mode, &base->icr); in i2c_reset()
84 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ in i2c_reset()
85 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */ in i2c_reset()
90 * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
101 isr = readl(&base->isr); in i2c_isr_set_cleared()
103 if (timeout-- < 0) in i2c_isr_set_cleared()
112 * i2c_transfer: - Transfer one byte over the i2c bus
118 * -1: message is empty
119 * -2: transmit timeout
120 * -3: ACK missing
121 * -4: receive timeout
122 * -5: illegal parameters
123 * -6: bus is busy and couldn't be aquired
132 switch (msg->direction) { in i2c_transfer()
134 /* check if bus is not busy */ in i2c_transfer()
139 writel(readl(&base->icr) & ~ICR_START, &base->icr); in i2c_transfer()
140 writel(readl(&base->icr) & ~ICR_STOP, &base->icr); in i2c_transfer()
141 writel(msg->data, &base->idbr); in i2c_transfer()
142 if (msg->condition == I2C_COND_START) in i2c_transfer()
143 writel(readl(&base->icr) | ICR_START, &base->icr); in i2c_transfer()
144 if (msg->condition == I2C_COND_STOP) in i2c_transfer()
145 writel(readl(&base->icr) | ICR_STOP, &base->icr); in i2c_transfer()
146 if (msg->acknack == I2C_ACKNAK_SENDNAK) in i2c_transfer()
147 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr); in i2c_transfer()
148 if (msg->acknack == I2C_ACKNAK_SENDACK) in i2c_transfer()
149 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr); in i2c_transfer()
150 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr); in i2c_transfer()
151 writel(readl(&base->icr) | ICR_TB, &base->icr); in i2c_transfer()
153 /* transmit register empty? */ in i2c_transfer()
157 /* clear 'transmit empty' state */ in i2c_transfer()
158 writel(readl(&base->isr) | ISR_ITE, &base->isr); in i2c_transfer()
161 if (msg->acknack == I2C_ACKNAK_WAITACK) in i2c_transfer()
168 /* check if bus is not busy */ in i2c_transfer()
173 writel(readl(&base->icr) & ~ICR_START, &base->icr); in i2c_transfer()
174 writel(readl(&base->icr) & ~ICR_STOP, &base->icr); in i2c_transfer()
175 if (msg->condition == I2C_COND_START) in i2c_transfer()
176 writel(readl(&base->icr) | ICR_START, &base->icr); in i2c_transfer()
177 if (msg->condition == I2C_COND_STOP) in i2c_transfer()
178 writel(readl(&base->icr) | ICR_STOP, &base->icr); in i2c_transfer()
179 if (msg->acknack == I2C_ACKNAK_SENDNAK) in i2c_transfer()
180 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr); in i2c_transfer()
181 if (msg->acknack == I2C_ACKNAK_SENDACK) in i2c_transfer()
182 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr); in i2c_transfer()
183 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr); in i2c_transfer()
184 writel(readl(&base->icr) | ICR_TB, &base->icr); in i2c_transfer()
190 msg->data = readl(&base->idbr); in i2c_transfer()
192 /* clear 'receive empty' state */ in i2c_transfer()
193 writel(readl(&base->isr) | ISR_IRF, &base->isr); in i2c_transfer()
202 debug("i2c_transfer: error: 'msg' is empty\n"); in i2c_transfer()
203 ret = -1; in i2c_transfer()
208 ret = -2; in i2c_transfer()
213 ret = -3; in i2c_transfer()
218 ret = -4; in i2c_transfer()
223 ret = -5; in i2c_transfer()
228 ret = -6; in i2c_transfer()
232 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr)); in i2c_transfer()
247 return -EINVAL; in __i2c_read()
260 return -1; in __i2c_read()
263 * send memory address bytes; in __i2c_read()
264 * alen defines how much bytes we have to send. in __i2c_read()
266 while (--alen >= 0) { in __i2c_read()
267 debug("i2c_read: send address byte %02x (alen=%d)\n", in __i2c_read()
274 return -1; in __i2c_read()
285 return -1; in __i2c_read()
287 /* read bytes; send NACK at last byte */ in __i2c_read()
288 while (len--) { in __i2c_read()
300 return -1; in __i2c_read()
331 return -1; in __i2c_write()
334 * send memory address bytes; in __i2c_write()
335 * alen defines how much bytes we have to send. in __i2c_write()
337 while (--alen >= 0) { in __i2c_write()
338 debug("i2c_read: send address byte %02x (alen=%d)\n", in __i2c_write()
345 return -1; in __i2c_write()
348 /* write bytes; send NACK at last byte */ in __i2c_write()
349 while (len--) { in __i2c_write()
363 return -1; in __i2c_write()
387 icr = readl(&base->icr); in i2c_board_init()
388 writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr); in i2c_board_init()
392 writel(icr, &base->icr); in i2c_board_init()
405 return -1; in i2c_set_bus_num()
441 clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val); in i2c_init()
457 return -1; in __i2c_probe_chip()
464 return -1; in __i2c_probe_chip()
470 * i2c_probe: - Test if a chip answers for a given i2c address
473 * @return: 0 if a chip was found, -1 otherwhise
481 * i2c_read: - Read multiple bytes from an i2c device
506 * i2c_write: - Write multiple bytes to an i2c device
549 return -1; in mv_i2c_xfer()
555 if (dmsg->flags & I2C_M_RD) in mv_i2c_xfer()
556 return __i2c_read(i2c->base, dmsg->addr, omsg->buf, in mv_i2c_xfer()
557 omsg->len, dmsg->buf, dmsg->len); in mv_i2c_xfer()
559 return __i2c_write(i2c->base, dmsg->addr, omsg->buf, in mv_i2c_xfer()
560 omsg->len, dmsg->buf, dmsg->len); in mv_i2c_xfer()
572 clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val); in mv_i2c_set_bus_speed()
581 priv->base = (void *)devfdt_get_addr_ptr(bus); in mv_i2c_probe()
592 { .compatible = "marvell,armada-3700-i2c" },