1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
34 	status = readl(&regs->msr);  in imx_lpci2c_check_busy_bus()
47 	status = readl(&regs->msr);  in imx_lpci2c_check_clear_error()
63 		writel(0x7f00, &regs->msr);  in imx_lpci2c_check_clear_error()
65 		val = readl(&regs->mcr);  in imx_lpci2c_check_clear_error()
67 		writel(val, &regs->mcr);  in imx_lpci2c_check_clear_error()
80 		txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));  in bus_i2c_wait_for_tx_ready()
81 		txcount = LPI2C_FIFO_SIZE - txcount;  in bus_i2c_wait_for_tx_ready()
89 			return -1;  in bus_i2c_wait_for_tx_ready()
105 	while (len--) {  in bus_i2c_send()
111 		writel(*txbuf++, &regs->mtdr);  in bus_i2c_send()
135 	writel(0x7f00, &regs->msr);  in bus_i2c_receive()
137 	val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);  in bus_i2c_receive()
138 	writel(val, &regs->mtdr);  in bus_i2c_receive()
140 	while (len--) {  in bus_i2c_receive()
150 				return -1;  in bus_i2c_receive()
152 			val = readl(&regs->mrdr);  in bus_i2c_receive()
171 		/* Try to init the lpi2c then check the bus busy again */  in bus_i2c_start()
180 	writel(0x7f00, &regs->msr);  in bus_i2c_start()
181 	/* turn off auto-stop condition */  in bus_i2c_start()
182 	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;  in bus_i2c_start()
183 	writel(val, &regs->mcfgr1);  in bus_i2c_start()
192 	writel(val, &regs->mtdr);  in bus_i2c_start()
212 	writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);  in bus_i2c_stop()
216 		status = readl(&regs->msr);  in bus_i2c_stop()
222 			writel(status, &regs->msr);  in bus_i2c_stop()
228 			return -ETIMEDOUT;  in bus_i2c_stop()
284 		clock_rate = clk_get_rate(&i2c_bus->per_clk);  in bus_i2c_set_bus_speed()
290 		clock_rate = imx_get_i2cclk(bus->seq);  in bus_i2c_set_bus_speed()
292 			return -EPERM;  in bus_i2c_set_bus_speed()
295 	mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;  in bus_i2c_set_bus_speed()
297 	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;  in bus_i2c_set_bus_speed()
298 	writel(val | LPI2C_MCR_MEN(0), &regs->mcr);  in bus_i2c_set_bus_speed()
308 			abs_error = speed > rate ? speed - rate : rate - speed;  in bus_i2c_set_bus_speed()
320 	/* Standard, fast, fast mode plus and ultra-fast transfers. */  in bus_i2c_set_bus_speed()
327 	writel(val, &regs->mccr0);  in bus_i2c_set_bus_speed()
336 	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;  in bus_i2c_set_bus_speed()
337 	writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);  in bus_i2c_set_bus_speed()
340 		val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;  in bus_i2c_set_bus_speed()
341 		writel(val | LPI2C_MCR_MEN(1), &regs->mcr);  in bus_i2c_set_bus_speed()
355 	writel(LPI2C_MCR_RST_MASK, &regs->mcr);  in bus_i2c_init()
356 	writel(0x0, &regs->mcr);  in bus_i2c_init()
358 	writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);  in bus_i2c_init()
360 	val = readl(&regs->mcfgr0);  in bus_i2c_init()
364 	writel(val, &regs->mcfgr0);  in bus_i2c_init()
366 	val = readl(&regs->mcfgr1);  in bus_i2c_init()
370 	writel(val, &regs->mcfgr1);  in bus_i2c_init()
374 	/* enable lpi2c in master mode */  in bus_i2c_init()
375 	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;  in bus_i2c_init()
376 	writel(val | LPI2C_MCR_MEN(1), &regs->mcr);  in bus_i2c_init()
378 	debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);  in bus_i2c_init()
406 	for (; nmsgs > 0; nmsgs--, msg++) {  in imx_lpi2c_xfer()
407 		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);  in imx_lpi2c_xfer()
408 		if (msg->flags & I2C_M_RD)  in imx_lpi2c_xfer()
409 			ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);  in imx_lpi2c_xfer()
411 			ret = bus_i2c_write(bus, msg->addr, msg->buf,  in imx_lpi2c_xfer()
412 					    msg->len);  in imx_lpi2c_xfer()
446 	i2c_bus->driver_data = dev_get_driver_data(bus);  in imx_lpi2c_probe()
450 		return -EINVAL;  in imx_lpi2c_probe()
452 	i2c_bus->base = addr;  in imx_lpi2c_probe()
453 	i2c_bus->index = bus->seq;  in imx_lpi2c_probe()
454 	i2c_bus->bus = bus;  in imx_lpi2c_probe()
457 	ret = init_i2c_power(bus->seq);  in imx_lpi2c_probe()
464 		ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);  in imx_lpi2c_probe()
469 		ret = clk_enable(&i2c_bus->per_clk);  in imx_lpi2c_probe()
475 		/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */  in imx_lpi2c_probe()
476 		ret = enable_i2c_clk(1, bus->seq);  in imx_lpi2c_probe()
486 	      bus->seq, i2c_bus->base,  in imx_lpi2c_probe()
487 	      i2c_bus->speed);  in imx_lpi2c_probe()
499 	{ .compatible = "fsl,imx7ulp-lpi2c", },
500 	{ .compatible = "fsl,imx8qm-lpi2c", },