Lines Matching +full:zynq +full:- +full:gpio +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq GPIO device driver
7 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
8 * Copyright (C) 2009 - 2014 Xilinx, Inc.
12 #include <asm/gpio.h>
44 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
45 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
47 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
48 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
50 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
51 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
53 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
54 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
56 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
57 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
59 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
61 /* Register offsets for the GPIO device */
62 /* LSW Mask & Data -WO */
64 /* MSW Mask & Data -WO */
66 /* Data Register-RW */
68 /* Direction mode reg-RW */
70 /* Output enable reg-RW */
72 /* Interrupt mask reg-RO */
74 /* Interrupt enable reg-WO */
76 /* Interrupt disable reg-WO */
78 /* Interrupt status reg-RO */
80 /* Interrupt type reg-RW */
82 /* Interrupt polarity reg-RW */
84 /* Interrupt on any, reg-RW */
93 /* GPIO upper 16 bit mask */
102 * struct zynq_platform_data - zynq gpio platform data structure
103 * @label: string to store in gpio->label
104 * @ngpio: max number of gpio pins
105 * @max_bank: maximum number of gpio banks
123 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
124 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
141 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
142 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
150 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
151 * for a given pin in the GPIO device
152 * @pin_num: gpio pin number within the device
153 * @bank_num: an output parameter used to return the bank number of the gpio
156 * for the given gpio pin
168 for (bank = 0; bank < platdata->p_data->max_bank; bank++) { in zynq_gpio_get_bank_pin()
169 if (pin_num >= platdata->p_data->bank_min[bank] && in zynq_gpio_get_bank_pin()
170 pin_num <= platdata->p_data->bank_max[bank]) { in zynq_gpio_get_bank_pin()
172 *bank_pin_num = pin_num - in zynq_gpio_get_bank_pin()
173 platdata->p_data->bank_min[bank]; in zynq_gpio_get_bank_pin()
178 if (bank >= platdata->p_data->max_bank) { in zynq_gpio_get_bank_pin()
185 static int gpio_is_valid(unsigned gpio, struct udevice *dev) in gpio_is_valid() argument
189 return gpio < platdata->p_data->ngpio; in gpio_is_valid()
192 static int check_gpio(unsigned gpio, struct udevice *dev) in check_gpio() argument
194 if (!gpio_is_valid(gpio, dev)) { in check_gpio()
195 printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); in check_gpio()
196 return -1; in check_gpio()
201 static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) in zynq_gpio_get_value() argument
207 if (check_gpio(gpio, dev) < 0) in zynq_gpio_get_value()
208 return -1; in zynq_gpio_get_value()
210 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); in zynq_gpio_get_value()
212 data = readl(platdata->base + in zynq_gpio_get_value()
215 return (data >> bank_pin_num) & 1; in zynq_gpio_get_value()
218 static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) in zynq_gpio_set_value() argument
223 if (check_gpio(gpio, dev) < 0) in zynq_gpio_set_value()
224 return -1; in zynq_gpio_set_value()
226 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); in zynq_gpio_set_value()
230 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; in zynq_gpio_set_value()
241 value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & in zynq_gpio_set_value()
244 writel(value, platdata->base + reg_offset); in zynq_gpio_set_value()
249 static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) in zynq_gpio_direction_input() argument
255 if (check_gpio(gpio, dev) < 0) in zynq_gpio_direction_input()
256 return -1; in zynq_gpio_direction_input()
258 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); in zynq_gpio_direction_input()
262 return -1; in zynq_gpio_direction_input()
265 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_input()
267 writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_input()
272 static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, in zynq_gpio_direction_output() argument
279 if (check_gpio(gpio, dev) < 0) in zynq_gpio_direction_output()
280 return -1; in zynq_gpio_direction_output()
282 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); in zynq_gpio_direction_output()
284 /* set the GPIO pin as output */ in zynq_gpio_direction_output()
285 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_output()
287 writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_output()
290 reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_direction_output()
292 writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_direction_output()
295 gpio_set_value(gpio, value); in zynq_gpio_direction_output()
306 return -1; in zynq_gpio_get_function()
310 /* set the GPIO pin as output */ in zynq_gpio_get_function()
311 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_get_function()
328 { .compatible = "xlnx,zynq-gpio-1.0",
330 { .compatible = "xlnx,zynqmp-gpio-1.0",
343 uc_priv->bank_name = strdup(label_ptr); in zynq_gpio_probe()
344 if (!uc_priv->bank_name) in zynq_gpio_probe()
345 return -ENOMEM; in zynq_gpio_probe()
347 uc_priv->bank_name = dev->name; in zynq_gpio_probe()
350 if (platdata->p_data) in zynq_gpio_probe()
351 uc_priv->gpio_count = platdata->p_data->ngpio; in zynq_gpio_probe()
360 platdata->base = (phys_addr_t)dev_read_addr(dev); in zynq_gpio_ofdata_to_platdata()
362 platdata->p_data = in zynq_gpio_ofdata_to_platdata()