drivers/gpio/tegra_gpio.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * NVIDIA Tegra20 GPIO handling.
4  *  (C) Copyright 2010-2012,2015
21 #include <asm/gpio.h>
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
33 	int base_gpio;		/* Port number for this port (0, 1,.., n-1) */
36 /* Information about each port at run-time */
39 	int base_gpio;		/* Port number for this port (0, 1,.., n-1) */
42 /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
43 static int get_config(unsigned gpio)  in get_config()  argument
46 	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];  in get_config()
50 	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);  in get_config()
51 	type = (u >> GPIO_BIT(gpio)) & 1;  in get_config()
54 		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");  in get_config()
59 /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
60 static void set_config(unsigned gpio, int type)  in set_config()  argument
63 	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];  in set_config()
67 		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");  in set_config()
69 	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);  in set_config()
71 		u |= 1 << GPIO_BIT(gpio);  in set_config()
73 		u &= ~(1 << GPIO_BIT(gpio));  in set_config()
74 	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);  in set_config()
77 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
78 static int get_direction(unsigned gpio)  in get_direction()  argument
81 	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];  in get_direction()
85 	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);  in get_direction()
86 	dir =  (u >> GPIO_BIT(gpio)) & 1;  in get_direction()
89 		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");  in get_direction()
94 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
95 static void set_direction(unsigned gpio, int output)  in set_direction()  argument
98 	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];  in set_direction()
102 		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");  in set_direction()
104 	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);  in set_direction()
106 		u |= 1 << GPIO_BIT(gpio);  in set_direction()
108 		u &= ~(1 << GPIO_BIT(gpio));  in set_direction()
109 	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);  in set_direction()
112 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
113 static void set_level(unsigned gpio, int high)  in set_level()  argument
116 	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];  in set_level()
120 		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);  in set_level()
122 	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);  in set_level()
124 		u |= 1 << GPIO_BIT(gpio);  in set_level()
126 		u &= ~(1 << GPIO_BIT(gpio));  in set_level()
127 	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);  in set_level()
134 /* set GPIO pin 'gpio' as an input */
139 	/* Configure GPIO direction as input. */  in tegra_gpio_direction_input()
140 	set_direction(state->base_gpio + offset, DIRECTION_INPUT);  in tegra_gpio_direction_input()
142 	/* Enable the pin as a GPIO */  in tegra_gpio_direction_input()
143 	set_config(state->base_gpio + offset, 1);  in tegra_gpio_direction_input()
148 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
153 	int gpio = state->base_gpio + offset;  in tegra_gpio_direction_output()  local
155 	/* Configure GPIO output value. */  in tegra_gpio_direction_output()
156 	set_level(gpio, value);  in tegra_gpio_direction_output()
158 	/* Configure GPIO direction as output. */  in tegra_gpio_direction_output()
159 	set_direction(gpio, DIRECTION_OUTPUT);  in tegra_gpio_direction_output()
161 	/* Enable the pin as a GPIO */  in tegra_gpio_direction_output()
162 	set_config(state->base_gpio + offset, 1);  in tegra_gpio_direction_output()
167 /* read GPIO IN value of pin 'gpio' */
171 	int gpio = state->base_gpio + offset;  in tegra_gpio_get_value()  local
175 	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));  in tegra_gpio_get_value()
177 	if (get_direction(gpio) == DIRECTION_INPUT)  in tegra_gpio_get_value()
178 		val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);  in tegra_gpio_get_value()
180 		val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);  in tegra_gpio_get_value()
182 	return (val >> GPIO_BIT(gpio)) & 1;  in tegra_gpio_get_value()
185 /* write GPIO OUT value to pin 'gpio' */
189 	int gpio = state->base_gpio + offset;  in tegra_gpio_set_value()  local
192 	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);  in tegra_gpio_set_value()
194 	/* Configure GPIO output value. */  in tegra_gpio_set_value()
195 	set_level(gpio, value);  in tegra_gpio_set_value()
200 void gpio_config_table(const struct tegra_gpio_config *config, int len)  in gpio_config_table()  argument
205 		switch (config[i].init) {  in gpio_config_table()
207 			set_direction(config[i].gpio, DIRECTION_INPUT);  in gpio_config_table()
210 			set_level(config[i].gpio, 0);  in gpio_config_table()
211 			set_direction(config[i].gpio, DIRECTION_OUTPUT);  in gpio_config_table()
214 			set_level(config[i].gpio, 1);  in gpio_config_table()
215 			set_direction(config[i].gpio, DIRECTION_OUTPUT);  in gpio_config_table()
218 		set_config(config[i].gpio, CONFIG_GPIO);  in gpio_config_table()
225 	int gpio = state->base_gpio + offset;  in tegra_gpio_get_function()  local
227 	if (!get_config(gpio))  in tegra_gpio_get_function()
229 	else if (get_direction(gpio))  in tegra_gpio_get_function()
238 	int gpio, port, ret;  in tegra_gpio_xlate()  local
240 	gpio = args->args[0];  in tegra_gpio_xlate()
241 	port = gpio / TEGRA_GPIOS_PER_PORT;  in tegra_gpio_xlate()
242 	ret = device_get_child(dev, port, &desc->dev);  in tegra_gpio_xlate()
245 	desc->offset = gpio % TEGRA_GPIOS_PER_PORT;  in tegra_gpio_xlate()
246 	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;  in tegra_gpio_xlate()
261  * Returns the name of a GPIO port
265  * @base_port: Base port number (0, 1..n-1)
285 	{ .compatible = "nvidia,tegra30-gpio" },
286 	{ .compatible = "nvidia,tegra20-gpio" },
293 	struct tegra_port_info *priv = dev->priv;  in gpio_tegra_probe()
294 	struct tegra_gpio_platdata *plat = dev->platdata;  in gpio_tegra_probe()
300 	priv->bank = plat->bank;  in gpio_tegra_probe()
301 	priv->base_gpio = plat->base_gpio;  in gpio_tegra_probe()
303 	uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;  in gpio_tegra_probe()
304 	uc_priv->bank_name = plat->port_name;  in gpio_tegra_probe()
310  * We have a top-level GPIO device with no actual GPIOs. It has a child
315 	struct tegra_gpio_platdata *plat = parent->platdata;  in gpio_tegra_bind()
335 	 * out the number of GPIO banks  in gpio_tegra_bind()
343 		return -EINVAL;  in gpio_tegra_bind()
356 				return -ENOMEM;  in gpio_tegra_bind()
357 			plat->bank = &ctlr->gpio_bank[bank];  in gpio_tegra_bind()
359 			plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;  in gpio_tegra_bind()
360 			plat->port_name = gpio_port_name(base_port);  in gpio_tegra_bind()
362 			ret = device_bind(parent, parent->driver,  in gpio_tegra_bind()
363 					  plat->port_name, plat, -1, &dev);  in gpio_tegra_bind()