1 // SPDX-License-Identifier: GPL-2.0+
6  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
11 #include <asm/arch-lpc32xx/cpu.h>
12 #include <asm/arch-lpc32xx/gpio.h>
13 #include <asm-generic/gpio.h>
17  * LPC32xx GPIOs work in banks but are non-homogeneous:
18  * - each bank holds a different number of GPIOs
19  * - some GPIOs are input/ouput, some input only, some output only;
20  * - some GPIOs have different meanings as an input and as an output;
21  * - some GPIOs are controlled on a given port and bit index, but
50  * - Port 0: 0
51  * - Port 1: 32
52  * - Port 2: 64
53  * - Port 3: GPO / GPIO (output): 96
54  * - Port 3: GPI: 128
71 	struct gpio_regs *regs = gpio_priv->regs;  in lpc32xx_gpio_direction_input()
78 		writel(mask, &regs->p0_dir_clr);  in lpc32xx_gpio_direction_input()
81 		writel(mask, &regs->p1_dir_clr);  in lpc32xx_gpio_direction_input()
85 		writel(mask, &regs->p2_p3_dir_clr);  in lpc32xx_gpio_direction_input()
88 		/* Setup direction only for GPIO_xx. */  in lpc32xx_gpio_direction_input()
90 			writel(mask, &regs->p2_p3_dir_clr);  in lpc32xx_gpio_direction_input()
96 		return -1;  in lpc32xx_gpio_direction_input()
100 	gpio_priv->function[offset] = GPIOF_INPUT;  in lpc32xx_gpio_direction_input()
113 	struct gpio_regs *regs = gpio_priv->regs;  in lpc32xx_gpio_get_value()
119 		value = readl(&regs->p0_inp_state);  in lpc32xx_gpio_get_value()
122 		value = readl(&regs->p1_inp_state);  in lpc32xx_gpio_get_value()
125 		value = readl(&regs->p2_inp_state);  in lpc32xx_gpio_get_value()
129 		value = readl(&regs->p3_outp_state);  in lpc32xx_gpio_get_value()
133 		value = readl(&regs->p3_inp_state);  in lpc32xx_gpio_get_value()
136 		return -1;  in lpc32xx_gpio_get_value()
153 	struct gpio_regs *regs = gpio_priv->regs;  in gpio_set()
160 		writel(mask, &regs->p0_outp_set);  in gpio_set()
163 		writel(mask, &regs->p1_outp_set);  in gpio_set()
166 		writel(mask, &regs->p2_outp_set);  in gpio_set()
169 		writel(mask, &regs->p3_outp_set);  in gpio_set()
174 		return -1;  in gpio_set()
187 	struct gpio_regs *regs = gpio_priv->regs;  in gpio_clr()
194 		writel(mask, &regs->p0_outp_clr);  in gpio_clr()
197 		writel(mask, &regs->p1_outp_clr);  in gpio_clr()
200 		writel(mask, &regs->p2_outp_clr);  in gpio_clr()
203 		writel(mask, &regs->p3_outp_clr);  in gpio_clr()
208 		return -1;  in gpio_clr()
235 	struct gpio_regs *regs = gpio_priv->regs;  in lpc32xx_gpio_direction_output()
242 		writel(mask, &regs->p0_dir_set);  in lpc32xx_gpio_direction_output()
245 		writel(mask, &regs->p1_dir_set);  in lpc32xx_gpio_direction_output()
249 		writel(mask, &regs->p2_p3_dir_set);  in lpc32xx_gpio_direction_output()
252 		/* Setup direction only for GPIO_xx. */  in lpc32xx_gpio_direction_output()
254 			writel(mask, &regs->p2_p3_dir_set);  in lpc32xx_gpio_direction_output()
259 		return -1;  in lpc32xx_gpio_direction_output()
263 	gpio_priv->function[offset] = GPIOF_OUTPUT;  in lpc32xx_gpio_direction_output()
284 	return gpio_priv->function[offset];  in lpc32xx_gpio_get_function()
298 	struct gpio_dev_priv *uc_priv = dev->uclass_priv;  in lpc32xx_gpio_probe()
300 	if (dev_of_offset(dev) == -1) {  in lpc32xx_gpio_probe()
302 		uc_priv->gpio_count = LPC32XX_GPIOS;  in lpc32xx_gpio_probe()
306 	gpio_priv->regs = (struct gpio_regs *)GPIO_BASE;  in lpc32xx_gpio_probe()
310 	memset(gpio_priv->function, GPIOF_UNKNOWN, sizeof(gpio_priv->function));  in lpc32xx_gpio_probe()