1 // SPDX-License-Identifier: GPL-2.0+
7  * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
9  * consisting of a standard header and a device-specific set of registers. PCI
17  *     PCI I/O space + [GPIOBASE]  => start of GPIO registers
18  *       GPIO registers => gpio pin function, direction, value
21  * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
36 #include <asm/gpio.h>
48 	uint16_t lvl;  member
62 	if (bank->use_lvl_write_cache)  in _ich6_gpio_set_value()
63 		val = bank->lvl_write_cache;  in _ich6_gpio_set_value()
65 		val = inl(bank->lvl);  in _ich6_gpio_set_value()
71 	outl(val, bank->lvl);  in _ich6_gpio_set_value()
72 	if (bank->use_lvl_write_cache)  in _ich6_gpio_set_value()
73 		bank->lvl_write_cache = val;  in _ich6_gpio_set_value()
102 	ret = pch_get_gpio_base(dev->parent, &gpiobase);  in gpio_ich6_ofdata_to_platdata()
106 	offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);  in gpio_ich6_ofdata_to_platdata()
107 	if (offset == -1) {  in gpio_ich6_ofdata_to_platdata()
109 		return -EINVAL;  in gpio_ich6_ofdata_to_platdata()
111 	plat->offset = offset;  in gpio_ich6_ofdata_to_platdata()
112 	plat->base_addr = gpiobase + offset;  in gpio_ich6_ofdata_to_platdata()
113 	plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),  in gpio_ich6_ofdata_to_platdata()
114 				      "bank-name", NULL);  in gpio_ich6_ofdata_to_platdata()
126 	uc_priv->gpio_count = GPIO_PER_BANK;  in ich6_gpio_probe()
127 	uc_priv->bank_name = plat->bank_name;  in ich6_gpio_probe()
128 	bank->use_sel = plat->base_addr;  in ich6_gpio_probe()
129 	bank->io_sel = plat->base_addr + 4;  in ich6_gpio_probe()
130 	bank->lvl = plat->base_addr + 8;  in ich6_gpio_probe()
132 	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),  in ich6_gpio_probe()
133 			   "use-lvl-write-cache", NULL);  in ich6_gpio_probe()
135 		bank->use_lvl_write_cache = true;  in ich6_gpio_probe()
137 		bank->use_lvl_write_cache = false;  in ich6_gpio_probe()
138 	bank->lvl_write_cache = 0;  in ich6_gpio_probe()
150 	 * Make sure that the GPIO pin we want isn't already in use for some  in ich6_gpio_request()
151 	 * built-in hardware function. We have to check this for every  in ich6_gpio_request()
154 	tmplong = inl(bank->use_sel);  in ich6_gpio_request()
156 		debug("%s: gpio %d is reserved for internal use\n", __func__,  in ich6_gpio_request()
158 		return -EPERM;  in ich6_gpio_request()
168 	return _ich6_gpio_set_direction(bank->io_sel, offset, 0);  in ich6_gpio_direction_input()
177 	ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);  in ich6_gpio_direction_output()
190 	tmplong = inl(bank->lvl);  in ich6_gpio_get_value()
191 	if (bank->use_lvl_write_cache)  in ich6_gpio_get_value()
192 		tmplong |= bank->lvl_write_cache;  in ich6_gpio_get_value()
209 	if (!(inl(bank->use_sel) & mask))  in ich6_gpio_get_function()
211 	if (inl(bank->io_sel) & mask)  in ich6_gpio_get_function()
227 	{ .compatible = "intel,ich6-gpio" },