48 	u32 mask;  in at91_set_port_pullup()  local
50 	mask = 1 << offset;  in at91_set_port_pullup()
52 		writel(mask, &at91_port->puer);  in at91_set_port_pullup()
54 		writel(mask, &at91_port->pudr);  in at91_set_port_pullup()
55 	writel(mask, &at91_port->per);  in at91_set_port_pullup()
74 	u32 mask;  in at91_set_pio_periph()  local
77 		mask = 1 << pin;  in at91_set_pio_periph()
78 		writel(mask, &at91_port->idr);  in at91_set_pio_periph()
80 		writel(mask, &at91_port->per);  in at91_set_pio_periph()
92 	u32 mask;  in at91_set_a_periph()  local
95 		mask = 1 << pin;  in at91_set_a_periph()
96 		writel(mask, &at91_port->idr);  in at91_set_a_periph()
98 		writel(mask, &at91_port->mux.pio2.asr);  in at91_set_a_periph()
99 		writel(mask, &at91_port->pdr);  in at91_set_a_periph()
111 	u32 mask;  in at91_set_b_periph()  local
114 		mask = 1 << pin;  in at91_set_b_periph()
115 		writel(mask, &at91_port->idr);  in at91_set_b_periph()
117 		writel(mask, &at91_port->mux.pio2.bsr);  in at91_set_b_periph()
118 		writel(mask, &at91_port->pdr);  in at91_set_b_periph()
130 	u32 mask;  in at91_pio3_set_a_periph()  local
133 		mask = 1 << pin;  in at91_pio3_set_a_periph()
134 		writel(mask, &at91_port->idr);  in at91_pio3_set_a_periph()
136 		writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,  in at91_pio3_set_a_periph()
138 		writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,  in at91_pio3_set_a_periph()
141 		writel(mask, &at91_port->pdr);  in at91_pio3_set_a_periph()
153 	u32 mask;  in at91_pio3_set_b_periph()  local
156 		mask = 1 << pin;  in at91_pio3_set_b_periph()
157 		writel(mask, &at91_port->idr);  in at91_pio3_set_b_periph()
159 		writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,  in at91_pio3_set_b_periph()
161 		writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,  in at91_pio3_set_b_periph()
164 		writel(mask, &at91_port->pdr);  in at91_pio3_set_b_periph()
175 	u32 mask;  in at91_pio3_set_c_periph()  local
178 		mask = 1 << pin;  in at91_pio3_set_c_periph()
179 		writel(mask, &at91_port->idr);  in at91_pio3_set_c_periph()
181 		writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,  in at91_pio3_set_c_periph()
183 		writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,  in at91_pio3_set_c_periph()
185 		writel(mask, &at91_port->pdr);  in at91_pio3_set_c_periph()
197 	u32 mask;  in at91_pio3_set_d_periph()  local
200 		mask = 1 << pin;  in at91_pio3_set_d_periph()
201 		writel(mask, &at91_port->idr);  in at91_pio3_set_d_periph()
203 		writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,  in at91_pio3_set_d_periph()
205 		writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,  in at91_pio3_set_d_periph()
207 		writel(mask, &at91_port->pdr);  in at91_pio3_set_d_periph()
216 	u32 mask, val;  in at91_get_port_output()  local
218 	mask = 1 << offset;  in at91_get_port_output()
220 	return val & mask;  in at91_get_port_output()
227 	u32 mask;  in at91_set_port_input()  local
229 	mask = 1 << offset;  in at91_set_port_input()
230 	writel(mask, &at91_port->idr);  in at91_set_port_input()
232 	writel(mask, &at91_port->odr);  in at91_set_port_input()
233 	writel(mask, &at91_port->per);  in at91_set_port_input()
253 	u32 mask;  in at91_set_port_output()  local
255 	mask = 1 << offset;  in at91_set_port_output()
256 	writel(mask, &at91_port->idr);  in at91_set_port_output()
257 	writel(mask, &at91_port->pudr);  in at91_set_port_output()
259 		writel(mask, &at91_port->sodr);  in at91_set_port_output()
261 		writel(mask, &at91_port->codr);  in at91_set_port_output()
262 	writel(mask, &at91_port->oer);  in at91_set_port_output()
263 	writel(mask, &at91_port->per);  in at91_set_port_output()
286 	u32 mask;  in at91_set_pio_deglitch()  local
289 		mask = 1 << pin;  in at91_set_pio_deglitch()
291 			writel(mask, &at91_port->ifer);  in at91_set_pio_deglitch()
293 			writel(mask, &at91_port->ifdr);  in at91_set_pio_deglitch()
305 	u32 mask;  in at91_pio3_set_pio_deglitch()  local
308 		mask = 1 << pin;  in at91_pio3_set_pio_deglitch()
310 			writel(mask, &at91_port->mux.pio3.ifscdr);  in at91_pio3_set_pio_deglitch()
311 			writel(mask, &at91_port->ifer);  in at91_pio3_set_pio_deglitch()
313 			writel(mask, &at91_port->ifdr);  in at91_pio3_set_pio_deglitch()
326 	u32 mask;  in at91_pio3_set_pio_debounce()  local
329 		mask = 1 << pin;  in at91_pio3_set_pio_debounce()
331 			writel(mask, &at91_port->mux.pio3.ifscer);  in at91_pio3_set_pio_debounce()
333 			writel(mask, &at91_port->ifer);  in at91_pio3_set_pio_debounce()
335 			writel(mask, &at91_port->ifdr);  in at91_pio3_set_pio_debounce()
349 	u32 mask;  in at91_pio3_set_pio_pulldown()  local
352 		mask = 1 << pin;  in at91_pio3_set_pio_pulldown()
355 			writel(mask, &at91_port->mux.pio3.ppder);  in at91_pio3_set_pio_pulldown()
357 			writel(mask, &at91_port->mux.pio3.ppddr);  in at91_pio3_set_pio_pulldown()
382 	u32 mask;  in at91_pio3_set_pio_disable_schmitt_trig()  local
385 		mask = 1 << pin;  in at91_pio3_set_pio_disable_schmitt_trig()
386 		writel(readl(&at91_port->schmitt) | mask,  in at91_pio3_set_pio_disable_schmitt_trig()
400 	u32 mask;  in at91_set_pio_multi_drive()  local
403 		mask = 1 << pin;  in at91_set_pio_multi_drive()
405 			writel(mask, &at91_port->mder);  in at91_set_pio_multi_drive()
407 			writel(mask, &at91_port->mddr);  in at91_set_pio_multi_drive()
416 	u32 mask;  in at91_set_port_value()  local
418 	mask = 1 << offset;  in at91_set_port_value()
420 		writel(mask, &at91_port->sodr);  in at91_set_port_value()
422 		writel(mask, &at91_port->codr);  in at91_set_port_value()
440 	u32 pdsr = 0, mask;  in at91_get_port_value()  local
442 	mask = 1 << offset;  in at91_get_port_value()
443 	pdsr = readl(&at91_port->pdsr) & mask;  in at91_get_port_value()