1 // SPDX-License-Identifier: BSD-3-Clause
24 	clrsetbits_le32(&fpgamgr_regs->ctrl,  in fpgamgr_set_cd_ratio()
29 /* Start the FPGA programming by initialize the FPGA Manager */
35 	msel = readl(&fpgamgr_regs->stat);  in fpgamgr_program_init()
44 		setbits_le32(&fpgamgr_regs->ctrl,  in fpgamgr_program_init()
59 		clrbits_le32(&fpgamgr_regs->ctrl,  in fpgamgr_program_init()
74 	/* To enable FPGA Manager configuration */  in fpgamgr_program_init()
75 	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);  in fpgamgr_program_init()
77 	/* To enable FPGA Manager drive over configuration line */  in fpgamgr_program_init()
78 	setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);  in fpgamgr_program_init()
80 	/* Put FPGA into reset phase */  in fpgamgr_program_init()
81 	setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);  in fpgamgr_program_init()
83 	/* (1) wait until FPGA enter reset phase */  in fpgamgr_program_init()
91 		puts("FPGA: Could not reset\n");  in fpgamgr_program_init()
92 		return -1;  in fpgamgr_program_init()
95 	/* Release FPGA from reset phase */  in fpgamgr_program_init()
96 	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);  in fpgamgr_program_init()
98 	/* (2) wait until FPGA enter configuration phase */  in fpgamgr_program_init()
106 		puts("FPGA: Could not configure\n");  in fpgamgr_program_init()
107 		return -2;  in fpgamgr_program_init()
111 	writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);  in fpgamgr_program_init()
114 	setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);  in fpgamgr_program_init()
119 /* Ensure the FPGA entering config done */
128 		reg = readl(&fpgamgr_regs->gpio_ext_porta);  in fpgamgr_program_poll_cd()
132 			printf("FPGA: Configuration error.\n");  in fpgamgr_program_poll_cd()
133 			return -3;  in fpgamgr_program_poll_cd()
143 		printf("FPGA: Timeout waiting for program.\n");  in fpgamgr_program_poll_cd()
144 		return -4;  in fpgamgr_program_poll_cd()
148 	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);  in fpgamgr_program_poll_cd()
153 /* Ensure the FPGA entering init phase */
160 		return -5;  in fpgamgr_program_poll_initphase()
162 	/* (4) wait until FPGA enter init phase or user mode */  in fpgamgr_program_poll_initphase()
172 		return -6;  in fpgamgr_program_poll_initphase()
177 /* Ensure the FPGA entering user mode */
184 		return -7;  in fpgamgr_program_poll_usermode()
186 	/* (5) wait until FPGA enter user mode */  in fpgamgr_program_poll_usermode()
193 		return -8;  in fpgamgr_program_poll_usermode()
195 	/* To release FPGA Manager drive over configuration line */  in fpgamgr_program_poll_usermode()
196 	clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);  in fpgamgr_program_poll_usermode()
202  * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
203  * Return 0 for sucess, non-zero for error.
210 		puts("FPGA: Unaligned data, realign to 32bit boundary.\n");  in socfpga_load()
211 		return -EINVAL;  in socfpga_load()
214 	/* Prior programming the FPGA, all bridges need to be shut off */  in socfpga_load()
216 	/* Disable all signals from hps peripheral controller to fpga */  in socfpga_load()
217 	writel(0, &sysmgr_regs->fpgaintfgrp_module);  in socfpga_load()
219 	/* Disable all signals from FPGA to HPS SDRAM */  in socfpga_load()
223 	/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */  in socfpga_load()
226 	/* Unmap the bridges from NIC-301 */  in socfpga_load()
229 	/* Initialize the FPGA Manager */  in socfpga_load()
234 	/* Write the RBF data to FPGA Manager */  in socfpga_load()
237 	/* Ensure the FPGA entering config done */  in socfpga_load()
242 	/* Ensure the FPGA entering init phase */  in socfpga_load()
247 	/* Ensure the FPGA entering user mode */  in socfpga_load()