Lines Matching +full:fpga +full:- +full:bridge
1 // SPDX-License-Identifier: GPL-2.0
37 reg = readl(&fpga_manager_base->imgcfg_stat); in fpgamgr_get_msel()
47 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()
50 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()
56 return (readl(&fpga_manager_base->imgcfg_stat) & in is_fpgamgr_user_mode()
62 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, in wait_for_user_mode()
69 return (readl(&fpga_manager_base->imgcfg_stat) & in is_fpgamgr_early_user_mode()
81 cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) & in fpgamgr_wait_early_user_mode()
90 return -ETIMEDOUT; in fpgamgr_wait_early_user_mode()
105 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
113 * de-asserted, timeout at 1000ms in wait_for_nconfig_pin_and_nstatus_pin()
115 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask, in wait_for_nconfig_pin_and_nstatus_pin()
122 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, in wait_for_f2s_nstatus_pin()
130 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cd_ratio()
133 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cd_ratio()
145 return -EPERM; in fpgamgr_verify_msel()
167 return -EINVAL; in fpgamgr_set_cdratio_cdwidth()
224 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_reset()
229 return -ETIME; in fpgamgr_reset()
232 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_reset()
237 return -ETIME; in fpgamgr_reset()
240 reg = readl(&fpga_manager_base->imgcfg_stat); in fpgamgr_reset()
242 return -EPERM; in fpgamgr_reset()
245 return -EPERM; in fpgamgr_reset()
250 /* Start the FPGA programming by initialize the FPGA Manager */
257 return -EPERM; in fpgamgr_program_init()
261 return -EPERM; in fpgamgr_program_init()
269 return -ETIME; in fpgamgr_program_init()
283 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
286 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
289 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_init()
293 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
296 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
306 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
308 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
316 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
324 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
329 return -ETIME; in fpgamgr_program_init()
341 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_init()
348 /* Ensure the FPGA entering config done */
354 reg = readl(&fpga_manager_base->imgcfg_stat); in fpgamgr_program_poll_cd()
360 return -EPERM; in fpgamgr_program_poll_cd()
365 return -ETIME; in fpgamgr_program_poll_cd()
370 /* Ensure the FPGA entering user mode */
377 return -ETIME; in fpgamgr_program_poll_usermode()
391 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_poll_usermode()
401 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
403 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_poll_usermode()
407 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
414 reg = readl(&fpga_manager_base->imgcfg_stat); in fpgamgr_program_poll_usermode()
421 return -EPERM; in fpgamgr_program_poll_usermode()
428 /* Ensure the FPGA entering config done */ in fpgamgr_program_finish()
432 printf("FPGA: Poll CD failed with error code %d\n", status); in fpgamgr_program_finish()
433 return -EPERM; in fpgamgr_program_finish()
437 /* Ensure the FPGA entering user mode */ in fpgamgr_program_finish()
440 printf("FPGA: Poll usermode failed with error code %d\n", in fpgamgr_program_finish()
442 return -EPERM; in fpgamgr_program_finish()
451 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
452 * Return 0 for sucess, non-zero for error.
458 /* disable all signals from hps peripheral controller to fpga */ in socfpga_load()
459 writel(0, &system_manager_base->fpgaintf_en_global); in socfpga_load()
461 /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ in socfpga_load()
464 /* Initialize the FPGA Manager */ in socfpga_load()
469 /* Write the RBF data to FPGA Manager */ in socfpga_load()