1 // SPDX-License-Identifier: GPL-2.0+
5  * @Descr: LPC3250 DMA controller interface support functions
7  * Copyright (c) 2015 Tyco Fire Protection Products.
12 #include <asm/arch/dma.h>
18 /* DMA controller channel register structure */
23 	u32 control;  member
28 /* DMA controller register structures */
51 #define DMAC_CTRL_ENABLE	(1 << 0) /* For enabling the DMA controller */
55 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;  variable
63 		 * DMA clock are enable by "lpc32xx_dma_init()" and should  in lpc32xx_dma_get_channel()
68 		 * Make sure DMA controller and all channels are disabled.  in lpc32xx_dma_get_channel()
69 		 * Controller is in little-endian mode. Disable sync signals.  in lpc32xx_dma_get_channel()
71 		writel(0, &dma->config);  in lpc32xx_dma_get_channel()
72 		writel(0, &dma->sync);  in lpc32xx_dma_get_channel()
75 		writel(0xFF, &dma->int_tc_clear);  in lpc32xx_dma_get_channel()
76 		writel(0xFF, &dma->raw_tc_stat);  in lpc32xx_dma_get_channel()
77 		writel(0xFF, &dma->int_err_clear);  in lpc32xx_dma_get_channel()
78 		writel(0xFF, &dma->raw_err_stat);  in lpc32xx_dma_get_channel()
80 		/* Enable DMA controller */  in lpc32xx_dma_get_channel()
81 		writel(DMAC_CTRL_ENABLE, &dma->config);  in lpc32xx_dma_get_channel()
88 		return -1;  in lpc32xx_dma_get_channel()
99 		return -1;  in lpc32xx_dma_start_xfer()
101 	writel(BIT_MASK(channel), &dma->int_tc_clear);  in lpc32xx_dma_start_xfer()
102 	writel(BIT_MASK(channel), &dma->int_err_clear);  in lpc32xx_dma_start_xfer()
103 	writel(desc->dma_src, &dma->dma_chan[channel].src_addr);  in lpc32xx_dma_start_xfer()
104 	writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);  in lpc32xx_dma_start_xfer()
105 	writel(desc->next_lli, &dma->dma_chan[channel].lli);  in lpc32xx_dma_start_xfer()
106 	writel(desc->next_ctrl, &dma->dma_chan[channel].control);  in lpc32xx_dma_start_xfer()
107 	writel(config, &dma->dma_chan[channel].config_ch);  in lpc32xx_dma_start_xfer()
120 		return -1;  in lpc32xx_dma_wait_status()
125 		reg = readl(&dma->raw_tc_stat);  in lpc32xx_dma_wait_status()
126 		reg |= readl(dma->raw_err_stat);  in lpc32xx_dma_wait_status()
131 			pr_err("DMA status timeout channel %d\n", channel);  in lpc32xx_dma_wait_status()
132 			return -ETIMEDOUT;  in lpc32xx_dma_wait_status()
137 	if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {  in lpc32xx_dma_wait_status()
138 		setbits_le32(&dma->int_err_clear, BIT_MASK(channel));  in lpc32xx_dma_wait_status()
139 		setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));  in lpc32xx_dma_wait_status()
140 		pr_err("DMA error on channel %d\n", channel);  in lpc32xx_dma_wait_status()
141 		return -1;  in lpc32xx_dma_wait_status()
143 	setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));  in lpc32xx_dma_wait_status()
144 	setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));  in lpc32xx_dma_wait_status()