Lines Matching refs:pup
49 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr,
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
108 for (pup = 0; in ddr3_write_leveling_hw()
109 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
110 pup++) { in ddr3_write_leveling_hw()
111 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
113 pup = ECC_PUP; in ddr3_write_leveling_hw()
116 pup); in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
127 cs, pup); in ddr3_write_leveling_hw()
128 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
137 for (pup = 0; in ddr3_write_leveling_hw()
138 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
139 pup++) { in ddr3_write_leveling_hw()
140 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
142 pup = ECC_PUP; in ddr3_write_leveling_hw()
144 DEBUG_WL_D((u32) pup, 1); in ddr3_write_leveling_hw()
147 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
151 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
292 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_wl_supplement()
294 pup_num = (ecc) ? ECC_PUP : pup; in ddr3_wl_supplement()
295 if (pup < 4) { /* lower 32 bit */ in ddr3_wl_supplement()
296 tmp_pup = pup; in ddr3_wl_supplement()
300 tmp_pup = pup - 4; in ddr3_wl_supplement()
317 + pup), 2); in ddr3_wl_supplement()
324 pup) - sdram_pup_val; in ddr3_wl_supplement()
332 pup); in ddr3_wl_supplement()
359 pup * (1 - ecc) + in ddr3_wl_supplement()
390 pup * (1 - ecc) + in ddr3_wl_supplement()
395 pup = (ecc) ? max_pup_num : pup; in ddr3_wl_supplement()
408 for (pup = 0; pup < dram_info->num_of_std_pups; pup++) in ddr3_wl_supplement()
409 sum += dram_info->wl_val[cs][pup][S]; in ddr3_wl_supplement()
432 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_wl_supplement()
433 if (pup == dram_info->num_of_std_pups in ddr3_wl_supplement()
435 pup = ECC_PUP; in ddr3_wl_supplement()
436 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
474 u32 reg, phase, delay, cs, pup, pup_num; in ddr3_write_leveling_hw_reg_dimm() local
488 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_hw_reg_dimm()
491 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup, in ddr3_write_leveling_hw_reg_dimm()
531 for (pup = 0; in ddr3_write_leveling_hw_reg_dimm()
532 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
533 pup++) { in ddr3_write_leveling_hw_reg_dimm()
534 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw_reg_dimm()
536 pup = ECC_BIT; in ddr3_write_leveling_hw_reg_dimm()
539 pup); in ddr3_write_leveling_hw_reg_dimm()
544 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
545 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw_reg_dimm()
552 cs, pup, 0, in ddr3_write_leveling_hw_reg_dimm()
554 dram_info->wl_val[cs][pup][P] = in ddr3_write_leveling_hw_reg_dimm()
556 dram_info->wl_val[cs][pup][D] = in ddr3_write_leveling_hw_reg_dimm()
559 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw_reg_dimm()
563 cs, pup); in ddr3_write_leveling_hw_reg_dimm()
564 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw_reg_dimm()
575 for (pup = 0; in ddr3_write_leveling_hw_reg_dimm()
576 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
577 pup++) { in ddr3_write_leveling_hw_reg_dimm()
580 DEBUG_WL_D((u32) pup, 1); in ddr3_write_leveling_hw_reg_dimm()
583 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
587 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
608 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
609 pup++) { in ddr3_write_leveling_hw_reg_dimm()
610 ddr3_write_ctrl_pup_reg(1, pup, in ddr3_write_leveling_hw_reg_dimm()
611 CNTRL_PUP_DESKEW + pup, 0); in ddr3_write_leveling_hw_reg_dimm()
620 for (pup = 0; in ddr3_write_leveling_hw_reg_dimm()
621 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
622 pup++) { in ddr3_write_leveling_hw_reg_dimm()
624 pup_num = (pup == dram_info->num_of_std_pups) ? in ddr3_write_leveling_hw_reg_dimm()
625 ECC_BIT : pup; in ddr3_write_leveling_hw_reg_dimm()
637 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
638 pup++) { in ddr3_write_leveling_hw_reg_dimm()
639 ddr3_write_ctrl_pup_reg(1, pup, in ddr3_write_leveling_hw_reg_dimm()
640 CNTRL_PUP_DESKEW + pup, 0); in ddr3_write_leveling_hw_reg_dimm()
659 u32 reg, cs, cnt, pup, max_pup_num; in ddr3_write_leveling_sw() local
773 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_write_leveling_sw()
774 if (((res[cs] >> pup) & 0x1) == 0) { in ddr3_write_leveling_sw()
776 pup, 1); in ddr3_write_leveling_sw()
884 u32 reg, cs, cnt, pup; in ddr3_write_leveling_sw_reg_dimm() local
904 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
907 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup, in ddr3_write_leveling_sw_reg_dimm()
1103 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
1104 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup, in ddr3_write_leveling_sw_reg_dimm()
1127 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup, in ddr3_write_leveling_single_cs() local
1262 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1264 pup_num = (pup == dram_info->num_of_std_pups) ? in ddr3_write_leveling_single_cs()
1265 ECC_BIT : pup; in ddr3_write_leveling_single_cs()
1266 if (dram_info->wl_val[cs][pup][S] == 0) { in ddr3_write_leveling_single_cs()
1268 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
1270 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_single_cs()
1278 && (dram_info->wl_val[cs][pup][S] == 0)) { in ddr3_write_leveling_single_cs()
1284 dram_info->wl_val[cs][pup][S] = 1; in ddr3_write_leveling_single_cs()
1301 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1303 DEBUG_WL_D((u32) pup, 1); in ddr3_write_leveling_single_cs()
1305 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1); in ddr3_write_leveling_single_cs()
1307 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2); in ddr3_write_leveling_single_cs()
1318 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1320 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_write_leveling_single_cs()
1321 phase = dram_info->wl_val[cs][pup][P]; in ddr3_write_leveling_single_cs()
1322 delay = dram_info->wl_val[cs][pup][D]; in ddr3_write_leveling_single_cs()
1338 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr, u32 data) in ddr3_write_ctrl_pup_reg() argument
1352 reg |= (pup << REG_PHY_PUP_OFFS); in ddr3_write_ctrl_pup_reg()