19 	DEBUG_WL_S(s); DEBUG_WL_D(d, l); DEBUG_WL_S("\n")
24 #define DEBUG_WL_S(s)			puts(s)  macro
31 #define DEBUG_WL_S(s)  macro
71 	DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n");  in ddr3_write_leveling_hw()
134 				DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - ");  in ddr3_write_leveling_hw()
136 				DEBUG_WL_S(" Results:\n");  in ddr3_write_leveling_hw()
143 					DEBUG_WL_S("DDR3 - Write Leveling - PUP: ");  in ddr3_write_leveling_hw()
145 					DEBUG_WL_S(", Phase: ");  in ddr3_write_leveling_hw()
149 					DEBUG_WL_S(", Delay: ");  in ddr3_write_leveling_hw()
153 					DEBUG_WL_S("\n");  in ddr3_write_leveling_hw()
168 		DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n");  in ddr3_write_leveling_hw()
172 		DEBUG_WL_S("DDR3 - Write Leveling - HW WL Error\n");  in ddr3_write_leveling_hw()
196 	DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Starting\n");  in ddr3_wl_supplement()
213 		DEBUG_WL_S("Error - bus width!!!\n");  in ddr3_wl_supplement()
224 	DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - SW Override Enabled\n");  in ddr3_wl_supplement()
240 						DEBUG_WL_S("ECC PUP:\n");  in ddr3_wl_supplement()
242 						DEBUG_WL_S("DATA PUP:\n");  in ddr3_wl_supplement()
284 							DEBUG_WL_S("\n");  in ddr3_wl_supplement()
288 						DEBUG_WL_S(" ");  in ddr3_wl_supplement()
305 						DEBUG_WL_S("\nCS: ");  in ddr3_wl_supplement()
307 						DEBUG_WL_S(" PUP: ");  in ddr3_wl_supplement()
309 						DEBUG_WL_S("\n");  in ddr3_wl_supplement()
356 							DEBUG_WL_S("#### Clock is longer than DQS more than one clk cycle ####\n");  in ddr3_wl_supplement()
372 							DEBUG_WL_S("#### Alignment PUPS problem ####\n");  in ddr3_wl_supplement()
377 								DEBUG_WL_S("#### Warning - Possible Layout Violation (DQS is longer than CLK)####\n");  in ddr3_wl_supplement()
459 	DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Ended Successfully\n");  in ddr3_wl_supplement()
478 	DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n");  in ddr3_write_leveling_hw_reg_dimm()
481 		DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n");  in ddr3_write_leveling_hw_reg_dimm()
572 				DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - ");  in ddr3_write_leveling_hw_reg_dimm()
574 				DEBUG_WL_S(" Results:\n");  in ddr3_write_leveling_hw_reg_dimm()
578 					DEBUG_WL_S  in ddr3_write_leveling_hw_reg_dimm()
581 					DEBUG_WL_S(", Phase: ");  in ddr3_write_leveling_hw_reg_dimm()
585 					DEBUG_WL_S(", Delay: ");  in ddr3_write_leveling_hw_reg_dimm()
589 					DEBUG_WL_S("\n");  in ddr3_write_leveling_hw_reg_dimm()
603 		DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n");  in ddr3_write_leveling_hw_reg_dimm()
644 		DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n");  in ddr3_write_leveling_hw_reg_dimm()
665 	DEBUG_WL_S("DDR3 - Write Leveling - Starting SW WL procedure\n");  in ddr3_write_leveling_sw()
889 	DEBUG_WL_S("DDR3 - Write Leveling - Starting SW WL procedure\n");  in ddr3_write_leveling_sw_reg_dimm()
1294 				DEBUG_WL_S("DDR3 - Write Leveling Single Cs - Seek Edge: All Locked\n");  in ddr3_write_leveling_single_cs()
1302 		DEBUG_WL_S("DDR3 - Write Leveling - PUP: ");  in ddr3_write_leveling_single_cs()
1304 		DEBUG_WL_S(", Phase: ");  in ddr3_write_leveling_single_cs()
1306 		DEBUG_WL_S(", Delay: ");  in ddr3_write_leveling_single_cs()
1308 		DEBUG_WL_S("\n");  in ddr3_write_leveling_single_cs()
1313 		DEBUG_WL_S("DDR3 - Write Leveling - ERROR - not all PUPS were locked\n");  in ddr3_write_leveling_single_cs()