Lines Matching full:cs
46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
106 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
115 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
127 cs, pup); in ddr3_write_leveling_hw()
128 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
133 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */ in ddr3_write_leveling_hw()
134 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw()
135 DEBUG_WL_D((u32) cs, 1); in ddr3_write_leveling_hw()
147 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
151 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
228 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
229 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
306 DEBUG_WL_D((u32) cs, 1); in ddr3_wl_supplement()
338 dram_info->wl_val[cs] in ddr3_wl_supplement()
345 [cs] in ddr3_wl_supplement()
349 dram_info->wl_val[cs] in ddr3_wl_supplement()
354 [cs][pup_num] in ddr3_wl_supplement()
358 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
366 [cs][pup_num] in ddr3_wl_supplement()
370 [cs][pup_num] in ddr3_wl_supplement()
382 dram_info->wl_val[cs] in ddr3_wl_supplement()
385 dram_info->wl_val[cs] in ddr3_wl_supplement()
389 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
409 sum += dram_info->wl_val[cs][pup][S]; in ddr3_wl_supplement()
412 sum += dram_info->wl_val[cs][ECC_PUP][S]; in ddr3_wl_supplement()
416 DEBUG_WL_C("DDR3 - Write Leveling Hi-Freq Supplement - didn't work for Cs - ", in ddr3_wl_supplement()
417 (u32) cs, 1); in ddr3_wl_supplement()
430 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
431 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
436 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
474 u32 reg, phase, delay, cs, pup, pup_num; in ddr3_write_leveling_hw_reg_dimm() local
529 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
530 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
538 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
544 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
545 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw_reg_dimm()
552 cs, pup, 0, in ddr3_write_leveling_hw_reg_dimm()
554 dram_info->wl_val[cs][pup][P] = in ddr3_write_leveling_hw_reg_dimm()
556 dram_info->wl_val[cs][pup][D] = in ddr3_write_leveling_hw_reg_dimm()
559 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw_reg_dimm()
563 cs, pup); in ddr3_write_leveling_hw_reg_dimm()
564 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw_reg_dimm()
569 * Debug message - Print res for cs[i]: in ddr3_write_leveling_hw_reg_dimm()
570 * cs,PUP,Phase,Delay in ddr3_write_leveling_hw_reg_dimm()
572 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw_reg_dimm()
573 DEBUG_WL_D((u32) cs, 1); in ddr3_write_leveling_hw_reg_dimm()
583 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
587 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
618 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
619 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
626 ddr3_write_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
659 u32 reg, cs, cnt, pup, max_pup_num; in ddr3_write_leveling_sw() local
677 /* Set Output buffer-off to all CS and correct ODT values */ in ddr3_write_leveling_sw()
678 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
679 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
682 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
687 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
689 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
692 * enable current cs in ddr3_write_leveling_sw()
701 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw()
720 /* Loop for each cs */ in ddr3_write_leveling_sw()
721 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
722 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
723 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Starting working with Cs - ", in ddr3_write_leveling_sw()
724 (u32) cs, 1); in ddr3_write_leveling_sw()
725 /* Refresh X9 current cs */ in ddr3_write_leveling_sw()
731 + cs)); in ddr3_write_leveling_sw()
732 /* [3-0] = 0x2 - refresh, [11-8] - enable current cs */ in ddr3_write_leveling_sw()
743 /* Configure MR1 in Cs[CsNum] - write leveling on, output buffer on */ in ddr3_write_leveling_sw()
744 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Configure MR1 for current Cs: WL-on,OB-on\n"); in ddr3_write_leveling_sw()
749 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
754 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
756 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
759 * enable current cs in ddr3_write_leveling_sw()
766 /* Write leveling cs[cs] */ in ddr3_write_leveling_sw()
768 ddr3_write_leveling_single_cs(cs, freq, ratio_2to1, in ddr3_write_leveling_sw()
769 (u32 *)(res + cs), in ddr3_write_leveling_sw()
771 DEBUG_WL_FULL_C("DDR3 - Write Leveling single Cs - FAILED - Cs - ", in ddr3_write_leveling_sw()
772 (u32) cs, 1); in ddr3_write_leveling_sw()
774 if (((res[cs] >> pup) & 0x1) == 0) { in ddr3_write_leveling_sw()
782 /* Set TrnWLDeUpd - After each CS is done */ in ddr3_write_leveling_sw()
789 * Debug message - Finished Write leveling cs[cs] - in ddr3_write_leveling_sw()
792 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw()
795 (u32) res[cs], 3); in ddr3_write_leveling_sw()
798 * Configure MR1 in cs[cs] - write leveling off (0), in ddr3_write_leveling_sw()
804 /* No need to sort ODT since it is same CS */ in ddr3_write_leveling_sw()
807 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
809 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
812 * enable current cs in ddr3_write_leveling_sw()
835 /* Set Output buffer-on to all CS and correct ODT values */ in ddr3_write_leveling_sw()
836 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
837 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
841 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
845 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
847 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
850 * enable current cs in ddr3_write_leveling_sw()
867 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Finished WL procedure for all Cs\n"); in ddr3_write_leveling_sw()
884 u32 reg, cs, cnt, pup; in ddr3_write_leveling_sw_reg_dimm() local
912 /* Set Output buffer-off to all CS and correct ODT values */ in ddr3_write_leveling_sw_reg_dimm()
913 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
914 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
917 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
922 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
924 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
927 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
936 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw_reg_dimm()
953 /* Loop for each cs */ in ddr3_write_leveling_sw_reg_dimm()
954 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
955 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
956 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Starting working with Cs - ", in ddr3_write_leveling_sw_reg_dimm()
957 (u32) cs, 1); in ddr3_write_leveling_sw_reg_dimm()
959 /* Refresh X9 current cs */ in ddr3_write_leveling_sw_reg_dimm()
965 + cs)); in ddr3_write_leveling_sw_reg_dimm()
966 /* [3-0] = 0x2 - refresh, [11-8] - enable current cs */ in ddr3_write_leveling_sw_reg_dimm()
978 * Configure MR1 in Cs[CsNum] - write leveling on, in ddr3_write_leveling_sw_reg_dimm()
981 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Configure MR1 for current Cs: WL-on,OB-on\n"); in ddr3_write_leveling_sw_reg_dimm()
986 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
995 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
997 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1000 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
1007 /* Write leveling cs[cs] */ in ddr3_write_leveling_sw_reg_dimm()
1009 ddr3_write_leveling_single_cs(cs, freq, ratio_2to1, in ddr3_write_leveling_sw_reg_dimm()
1010 (u32 *)(res + cs), in ddr3_write_leveling_sw_reg_dimm()
1012 DEBUG_WL_FULL_C("DDR3 - Write Leveling single Cs - FAILED - Cs - ", in ddr3_write_leveling_sw_reg_dimm()
1013 (u32) cs, 1); in ddr3_write_leveling_sw_reg_dimm()
1017 /* Set TrnWLDeUpd - After each CS is done */ in ddr3_write_leveling_sw_reg_dimm()
1024 * Debug message - Finished Write leveling cs[cs] - in ddr3_write_leveling_sw_reg_dimm()
1027 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw_reg_dimm()
1030 (u32) res[cs], 3); in ddr3_write_leveling_sw_reg_dimm()
1032 /* Configure MR1 in cs[cs] - write leveling off (0), output buffer off (1) */ in ddr3_write_leveling_sw_reg_dimm()
1036 /* No need to sort ODT since it is same CS */ in ddr3_write_leveling_sw_reg_dimm()
1039 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
1041 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1044 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
1067 /* Set Output buffer-on to all CS and correct ODT values */ in ddr3_write_leveling_sw_reg_dimm()
1068 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
1069 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
1073 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
1077 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
1079 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1082 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
1109 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Finished WL procedure for all Cs\n"); in ddr3_write_leveling_sw_reg_dimm()
1117 * Args: cs - current chip select
1124 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, in ddr3_write_leveling_single_cs() argument
1134 DEBUG_WL_FULL_C("DDR3 - Write Leveling Single Cs - WL for Cs - ", in ddr3_write_leveling_single_cs()
1135 (u32) cs, 1); in ddr3_write_leveling_single_cs()
1163 /* CS ODT Override */ in ddr3_write_leveling_single_cs()
1166 reg |= (REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA << (2 * cs)); in ddr3_write_leveling_single_cs()
1167 /* Set 0x3 - Enable ODT on the curent cs and disable on other cs */ in ddr3_write_leveling_single_cs()
1171 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - ODT Asserted for current Cs\n"); in ddr3_write_leveling_single_cs()
1177 /* [1:0] - current cs number */ in ddr3_write_leveling_single_cs()
1178 reg = (reg_read(REG_TRAINING_WL_ADDR) & REG_TRAINING_WL_CS_MASK) | cs; in ddr3_write_leveling_single_cs()
1184 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, 0, 0); in ddr3_write_leveling_single_cs()
1187 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Current Cs\n"); in ddr3_write_leveling_single_cs()
1190 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Driving DQS high for one cycle\n"); in ddr3_write_leveling_single_cs()
1218 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Shift DQS + Octet Leveling\n"); in ddr3_write_leveling_single_cs()
1224 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, phase, in ddr3_write_leveling_single_cs()
1229 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge: Phase = "); in ddr3_write_leveling_single_cs()
1258 DEBUG_WL_FULL_C("DDR3 - Write Leveling Single Cs - Seek Edge: Results = ", in ddr3_write_leveling_single_cs()
1266 if (dram_info->wl_val[cs][pup][S] == 0) { in ddr3_write_leveling_single_cs()
1268 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
1270 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_single_cs()
1278 && (dram_info->wl_val[cs][pup][S] == 0)) { in ddr3_write_leveling_single_cs()
1284 dram_info->wl_val[cs][pup][S] = 1; in ddr3_write_leveling_single_cs()
1294 DEBUG_WL_S("DDR3 - Write Leveling Single Cs - Seek Edge: All Locked\n"); in ddr3_write_leveling_single_cs()
1299 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */ in ddr3_write_leveling_single_cs()
1300 DEBUG_WL_C("DDR3 - Write Leveling - Results for CS - ", (u32) cs, 1); in ddr3_write_leveling_single_cs()
1305 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1); in ddr3_write_leveling_single_cs()
1307 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2); in ddr3_write_leveling_single_cs()
1321 phase = dram_info->wl_val[cs][pup][P]; in ddr3_write_leveling_single_cs()
1322 delay = dram_info->wl_val[cs][pup][D]; in ddr3_write_leveling_single_cs()
1323 ddr3_write_pup_reg(PUP_WL_MODE, cs, pup_num, phase, delay); in ddr3_write_leveling_single_cs()
1326 /* CS ODT Override */ in ddr3_write_leveling_single_cs()